[CodeGen] Ensure split interval has valid ranges for all sub registers

Authored by dstuttard on Jun 25 2018, 6:21 AM.



The issue comes about due to an interval split (a prelude to adding a
spill). The insertion of the spill is the point at which the assertion is
triggered, but it is the initial interval split that causes the error state.

A split is created by adding 2 new virtual registers and a copy from one to the
other at the split point. In this case, the register being split has
sub-registers and one of the lanes is never defined (other than with an

Inserting the copy causes a new use of the undefined lane and the copy is
inserted in a block with multiple predecessors. One of these predecessors has a
partial def (copy to one of the lanes) and is marked as undef which means that
the non-written lane is undefined. This is valid when there are no uses and the
original def is an IMPLICIT_DEF, but by adding the new use in the split copy,
this causes issues during the phase to extend uses during the split.

This fix detects a situation where it ignores any tagged
undefs in partial copies and traces back to any dead defs - if these are
confirmed then it treats the whole lane as dead and doesn't add the live range
to the newly created split register - this resolves the assertion.

There may be other more complicated cases with larger numbers of predecessors
that still break but are extremely unlikely to exhibit this issue.

See the comment in the lit test for an example of the problem (simplified in the

Diff Detail

dstuttard created this revision.Jun 25 2018, 6:21 AM
kparzysz added inline comments.Jun 25 2018, 11:59 AM

This situation is actually legitimate, and the existing code should be handling this already. It seems like the assertion itself may be incorrect.


Please reduce .mir testcases. Most of this stuff is unnecessary, the register classes in particular.

Please consider D48555 as a fix.

dstuttard abandoned this revision.Jun 26 2018, 3:01 AM

D48555 supersedes this change.