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Differential D48335

[DAG] Fix and-mask folding when narrowing loads.
ClosedPublic

Authored by niravd on Jun 19 2018, 2:04 PM.

Details

Reviewers
samparker
RKSimon
nemanjai
Commits
rGcd558887d3b1: [DAG] Fix and-mask folding when narrowing loads.
rL335137: [DAG] Fix and-mask folding when narrowing loads.
Summary

Check that and masks are strictly smaller than implicit mask from
narrowed load.

Fixes PR37820.

Diff Detail

Repository
rL LLVM

Event Timeline

niravd created this revision.Jun 19 2018, 2:04 PM
Herald added a subscriber: hiraditya. · View Herald TranscriptJun 19 2018, 2:04 PM
Harbormaster completed remote builds in B19481: Diff 151974.Jun 19 2018, 2:04 PM
samparker accepted this revision.Jun 20 2018, 12:36 AM

LGTM. Thanks.

This revision is now accepted and ready to land.Jun 20 2018, 12:36 AM
Closed by commit rL335137: [DAG] Fix and-mask folding when narrowing loads. (authored by niravd). · Explain WhyJun 20 2018, 8:40 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
SelectionDAG/
5 lines
test/
CodeGen/
X86/
25 lines

Diff 152097

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 8,682 Lines • ▼ Show 20 Lines if (auto *ConstShift = dyn_cast<ConstantSDNode>(SRL.getOperand(1))) {
SDNode *Mask = *(SRL->use_begin()); SDNode *Mask = *(SRL->use_begin());
if (Mask->getOpcode() == ISD::AND && if (Mask->getOpcode() == ISD::AND &&
isa<ConstantSDNode>(Mask->getOperand(1))) { isa<ConstantSDNode>(Mask->getOperand(1))) {
const APInt &ShiftMask = const APInt &ShiftMask =
cast<ConstantSDNode>(Mask->getOperand(1))->getAPIntValue(); cast<ConstantSDNode>(Mask->getOperand(1))->getAPIntValue();
if (ShiftMask.isMask()) { if (ShiftMask.isMask()) {
EVT MaskedVT = EVT::getIntegerVT(*DAG.getContext(), EVT MaskedVT = EVT::getIntegerVT(*DAG.getContext(),
ShiftMask.countTrailingOnes()); ShiftMask.countTrailingOnes());
// Recompute the type. // If the mask is smaller, recompute the type.
if (TLI.isLoadExtLegal(ExtType, N0.getValueType(), MaskedVT)) if ((ExtVT.getSizeInBits() > MaskedVT.getSizeInBits()) &&
TLI.isLoadExtLegal(ExtType, N0.getValueType(), MaskedVT))
ExtVT = MaskedVT; ExtVT = MaskedVT;
} }
} }
} }
} }
// If the load is shifted left (and the result isn't shifted back right), // If the load is shifted left (and the result isn't shifted back right),
// we can fold the truncate through the shift. // we can fold the truncate through the shift.
▲ Show 20 Lines • Show All 9,520 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/pr37820.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-linux-gnu %s -o - | FileCheck %s
@a = external dso_local local_unnamed_addr global i64, align 8
@c = external dso_local local_unnamed_addr global i64, align 8
@b = external dso_local local_unnamed_addr global i64, align 8
; Should generate a 16-bit load
define void @foo() {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movzwl a+{{.*}}(%rip), %eax
; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: retq
entry:
%0 = load i64, i64* @a, align 8
%1 = load i64, i64* @c, align 8
%and = and i64 %1, -16384
%add = add nsw i64 %and, 4503359447364223024
%shr = lshr i64 %0, %add
%conv1 = and i64 %shr, 4294967295
store i64 %conv1, i64* @b, align 8
ret void
}