[llvm-exegesis] Use a Prototype to defer picking a value for free vars.

[gchatelet]

Summary

Introducing a Prototype object to capture Variables that must be set but keeps degrees of freedom as Invalid. This allows exploring non constraint variables later on.

[courbet]

tools/llvm-exegesis/lib/MCInstrDescView.cpp

131

?

tools/llvm-exegesis/lib/MCInstrDescView.h

91

[nit] noexcept

91

class InstructionInstance {

InstructionInstance(InstructionInstance&&) noexcept;

};

inline InstructionInstance::InstructionInstance(InstructionInstance&&) noexcept = default;

To force the compiler to actually generate the code.

103

Did you want to add this is a separate patch ? It's not called and not implemented.

121

ditto

[gchatelet]

Addressed comments.

tools/llvm-exegesis/lib/BenchmarkRunner.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_EXEGESIS_BENCHMARKRUNNER_H
 #define LLVM_TOOLS_LLVM_EXEGESIS_BENCHMARKRUNNER_H
 
 #include "Assembler.h"
 #include "BenchmarkResult.h"
 #include "LlvmState.h"
+#include "MCInstrDescView.h"
 #include "RegisterAliasing.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/Support/Error.h"
 #include <vector>
 
 namespace exegesis {
 
 // A class representing failures that happened during Benchmark, they are used
protected:
   const llvm::MCInstrInfo &MCInstrInfo;
   const llvm::MCRegisterInfo &MCRegisterInfo;
   const RegisterAliasingTrackerCache RATC;
 
 private:
   InstructionBenchmark runOne(const BenchmarkConfiguration &Configuration,
                               unsigned Opcode, unsigned NumRepetitions) const;
 
+  // Calls generatePrototype and expands the SnippetPrototype into one or more
+  // BenchmarkConfiguration.
+  llvm::Expected<std::vector<BenchmarkConfiguration>>
+  generateConfigurations(unsigned Opcode) const;
+
   virtual InstructionBenchmark::ModeE getMode() const = 0;
 
-  virtual llvm::Expected<std::vector<BenchmarkConfiguration>>
-  createConfigurations(unsigned Opcode) const = 0;
+  virtual llvm::Expected<SnippetPrototype>
+  generatePrototype(unsigned Opcode) const = 0;
 
   virtual std::vector<BenchmarkMeasure>
   runMeasurements(const ExecutableFunction &EF,
                   const unsigned NumRepetitions) const = 0;
 
   llvm::Expected<std::string>
   writeObjectFile(llvm::ArrayRef<llvm::MCInst> Code) const;
   llvm::Expected<ExecutableFunction>
   createExecutableFunction(llvm::ArrayRef<llvm::MCInst> Code) const;
 };
 
 } // namespace exegesis
 
 #endif // LLVM_TOOLS_LLVM_EXEGESIS_BENCHMARKRUNNER_H

tools/llvm-exegesis/lib/BenchmarkRunner.cpp

BenchmarkRunner::run(unsigned Opcode, const InstructionFilter &Filter,
   // Ignore instructions that we cannot run.
   if (State.getInstrInfo().get(Opcode).isPseudo())
     return llvm::make_error<BenchmarkFailure>("Unsupported opcode: isPseudo");
 
   if (llvm::Error E = Filter.shouldRun(State, Opcode))
     return std::move(E);
 
   llvm::Expected<std::vector<BenchmarkConfiguration>> ConfigurationOrError =
-      createConfigurations(Opcode);
+      generateConfigurations(Opcode);
 
   if (llvm::Error E = ConfigurationOrError.takeError())
     return std::move(E);
 
   std::vector<InstructionBenchmark> InstrBenchmarks;
   for (const BenchmarkConfiguration &Conf : ConfigurationOrError.get())
     InstrBenchmarks.push_back(runOne(Conf, Opcode, NumRepetitions));
   return InstrBenchmarks;
if (llvm::Error E = EF.takeError()) {
     InstrBenchmark.Error = llvm::toString(std::move(E));
     return InstrBenchmark;
   }
   InstrBenchmark.Measurements = runMeasurements(*EF, NumRepetitions);
 
   return InstrBenchmark;
 }
 
+llvm::Expected<std::vector<BenchmarkConfiguration>>
+BenchmarkRunner::generateConfigurations(unsigned Opcode) const {
+  if (auto E = generatePrototype(Opcode)) {
+    SnippetPrototype &Prototype = E.get();
+    // TODO: Generate as many configurations as needed here.
+    BenchmarkConfiguration Configuration;
+    Configuration.Info = Prototype.Explanation;
+    for (InstructionInstance &II : Prototype.Snippet)
+      Configuration.Snippet.push_back(II.randomizeUnsetVariablesAndBuild());
+    return std::vector<BenchmarkConfiguration>{Configuration};
+  } else
+    return E.takeError();
+}
+
 llvm::Expected<std::string>
 BenchmarkRunner::writeObjectFile(llvm::ArrayRef<llvm::MCInst> Code) const {
   int ResultFD = 0;
   llvm::SmallString<256> ResultPath;
   if (llvm::Error E = llvm::errorCodeToError(llvm::sys::fs::createTemporaryFile(
           "snippet", "o", ResultFD, ResultPath)))
     return std::move(E);
   llvm::raw_fd_ostream OFS(ResultFD, true /*ShouldClose*/);

tools/llvm-exegesis/lib/Latency.h

 
 namespace exegesis {
 
 class LatencyBenchmarkRunner : public BenchmarkRunner {
 public:
   using BenchmarkRunner::BenchmarkRunner;
   ~LatencyBenchmarkRunner() override;
 
-  llvm::Expected<BenchmarkConfiguration>
-  generateConfiguration(unsigned Opcode) const;
+  llvm::Expected<SnippetPrototype>
+  generatePrototype(unsigned Opcode) const override;
 
 private:
   llvm::Error isInfeasible(const llvm::MCInstrDesc &MCInstrDesc) const;
 
-  llvm::Expected<BenchmarkConfiguration> generateSelfAliasingConfiguration(
+  llvm::Expected<SnippetPrototype> generateSelfAliasingPrototype(
       const Instruction &Instr,
       const AliasingConfigurations &SelfAliasing) const;
 
-  llvm::Expected<BenchmarkConfiguration> generateTwoInstructionConfiguration(
+  llvm::Expected<SnippetPrototype> generateTwoInstructionPrototype(
       const Instruction &Instr,
       const AliasingConfigurations &SelfAliasing) const;
 
   InstructionBenchmark::ModeE getMode() const override;
 
-  llvm::Expected<std::vector<BenchmarkConfiguration>>
-  createConfigurations(unsigned OpcodeIndex) const override;
-
   std::vector<BenchmarkMeasure>
   runMeasurements(const ExecutableFunction &EF,
                   const unsigned NumRepetitions) const override;
 };
 
 } // namespace exegesis
 
 #endif // LLVM_TOOLS_LLVM_EXEGESIS_LATENCY_H

tools/llvm-exegesis/lib/Latency.cpp

 
 #include "Assembler.h"
 #include "BenchmarkRunner.h"
 #include "MCInstrDescView.h"
 #include "PerfHelper.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstBuilder.h"
+#include "llvm/Support/FormatVariadic.h"
 
 namespace exegesis {
 
 static bool hasUnknownOperand(const llvm::MCOperandInfo &OpInfo) {
   return OpInfo.OperandType == llvm::MCOI::OPERAND_UNKNOWN;
 }
 
 // FIXME: Handle memory, see PR36905.
if (llvm::any_of(MCInstrDesc.operands(), hasUnknownOperand))
     return llvm::make_error<BenchmarkFailure>(
         "Infeasible : has unknown operands");
   if (llvm::any_of(MCInstrDesc.operands(), hasMemoryOperand))
     return llvm::make_error<BenchmarkFailure>(
         "Infeasible : has memory operands");
   return llvm::Error::success();
 }
 
-llvm::Expected<BenchmarkConfiguration>
-LatencyBenchmarkRunner::generateSelfAliasingConfiguration(
+llvm::Expected<SnippetPrototype>
+LatencyBenchmarkRunner::generateSelfAliasingPrototype(
     const Instruction &Instr,
     const AliasingConfigurations &SelfAliasing) const {
-  BenchmarkConfiguration Conf;
+  SnippetPrototype Prototype;
   InstructionInstance II(Instr);
   if (SelfAliasing.hasImplicitAliasing()) {
-    Conf.Info = "implicit Self cycles, picking random values.";
+    Prototype.Explanation = "implicit Self cycles, picking random values.";
   } else {
-    Conf.Info = "explicit self cycles, selecting one aliasing Conf.";
+    Prototype.Explanation =
+        "explicit self cycles, selecting one aliasing Conf.";
     // This is a self aliasing instruction so defs and uses are from the same
     // instance, hence twice II in the following call.
     setRandomAliasing(SelfAliasing, II, II);
   }
-  Conf.Snippet = {II.randomizeUnsetVariablesAndBuild()};
-  return Conf;
+  Prototype.Snippet.push_back(std::move(II));
+  return Prototype;
 }
 
-llvm::Expected<BenchmarkConfiguration>
-LatencyBenchmarkRunner::generateTwoInstructionConfiguration(
+llvm::Expected<SnippetPrototype>
+LatencyBenchmarkRunner::generateTwoInstructionPrototype(
     const Instruction &Instr,
     const AliasingConfigurations &SelfAliasing) const {
   std::vector<unsigned> Opcodes;
   Opcodes.resize(MCInstrInfo.getNumOpcodes());
   std::iota(Opcodes.begin(), Opcodes.end(), 0U);
   std::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator());
   for (const unsigned OtherOpcode : Opcodes) {
-    if (OtherOpcode == Instr.Description.Opcode)
+    if (OtherOpcode == Instr.Description->Opcode)
       continue;
     const auto &OtherInstrDesc = MCInstrInfo.get(OtherOpcode);
     if (auto E = isInfeasible(OtherInstrDesc)) {
       llvm::consumeError(std::move(E));
       continue;
     }
     const Instruction OtherInstr(OtherInstrDesc, RATC);
     const AliasingConfigurations Forward(Instr, OtherInstr);
     const AliasingConfigurations Back(OtherInstr, Instr);
     if (Forward.empty() || Back.empty())
       continue;
     InstructionInstance ThisII(Instr);
     InstructionInstance OtherII(OtherInstr);
     if (!Forward.hasImplicitAliasing())
       setRandomAliasing(Forward, ThisII, OtherII);
     if (!Back.hasImplicitAliasing())
       setRandomAliasing(Back, OtherII, ThisII);
-    BenchmarkConfiguration Conf;
-    Conf.Info = llvm::Twine("creating cycle through ")
-                    .concat(MCInstrInfo.getName(OtherOpcode))
-                    .concat(".")
-                    .str();
-    Conf.Snippet.push_back(ThisII.randomizeUnsetVariablesAndBuild());
-    Conf.Snippet.push_back(OtherII.randomizeUnsetVariablesAndBuild());
-    return Conf;
+    SnippetPrototype Prototype;
+    Prototype.Explanation = llvm::formatv("creating cycle through {0}.",
+                                          MCInstrInfo.getName(OtherOpcode));
+    Prototype.Snippet.push_back(std::move(ThisII));
+    Prototype.Snippet.push_back(std::move(OtherII));
+    return Prototype;
   }
   return llvm::make_error<BenchmarkFailure>(
       "Infeasible : Didn't find any scheme to make the instruction serial");
 }
 
-llvm::Expected<BenchmarkConfiguration>
-LatencyBenchmarkRunner::generateConfiguration(unsigned Opcode) const {
+llvm::Expected<SnippetPrototype>
+LatencyBenchmarkRunner::generatePrototype(unsigned Opcode) const {
   const auto &InstrDesc = MCInstrInfo.get(Opcode);
   if (auto E = isInfeasible(InstrDesc))
     return std::move(E);
   const Instruction Instr(InstrDesc, RATC);
   const AliasingConfigurations SelfAliasing(Instr, Instr);
   if (SelfAliasing.empty()) {
     // No self aliasing, trying to create a dependency through another opcode.
-    return generateTwoInstructionConfiguration(Instr, SelfAliasing);
+    return generateTwoInstructionPrototype(Instr, SelfAliasing);
   } else {
-    return generateSelfAliasingConfiguration(Instr, SelfAliasing);
+    return generateSelfAliasingPrototype(Instr, SelfAliasing);
   }
 }
 
-llvm::Expected<std::vector<BenchmarkConfiguration>>
-LatencyBenchmarkRunner::createConfigurations(unsigned Opcode) const {
-  if (auto E = generateConfiguration(Opcode))
-    return std::vector<BenchmarkConfiguration>{E.get()};
-  else
-    return E.takeError();
-}
-
 std::vector<BenchmarkMeasure>
 LatencyBenchmarkRunner::runMeasurements(const ExecutableFunction &Function,
                                         const unsigned NumRepetitions) const {
   // Cycle measurements include some overhead from the kernel. Repeat the
   // measure several times and take the minimum value.
   constexpr const int NumMeasurements = 30;
   int64_t MinLatency = std::numeric_limits<int64_t>::max();
   const char *CounterName = State.getSubtargetInfo()

tools/llvm-exegesis/lib/MCInstrDescView.h

 
 namespace exegesis {
 
 struct Operand; // forward declaration.
 
 // A variable represents the value associated to an Operand or a set of Operands
 // if they are tied together.
 struct Variable {
-  llvm::SmallVector<const Operand *, 2> TiedOperands;
+  // The indices of the operands tied to this Variable.
+  llvm::SmallVector<unsigned, 2> TiedOperands;
   llvm::MCOperand AssignedValue;
   // The index of this Variable in Instruction.Variables and its associated
   // Value in InstructionInstance.VariableValues.
   unsigned Index = -1;
 };
 
 // MCOperandInfo can only represents Explicit operands. This object gives a
 // uniform view of Implicit and Explicit Operands.

 };
 
 // A view over an MCInstrDesc offering a convenient interface to compute
 // Register aliasing.
 struct Instruction {
   Instruction(const llvm::MCInstrDesc &MCInstrDesc,
               const RegisterAliasingTrackerCache &ATC);
 
-  const llvm::MCInstrDesc &Description;
+  const llvm::MCInstrDesc *Description = nullptr;
   llvm::SmallVector<Operand, 8> Operands;
   llvm::SmallVector<Variable, 4> Variables;
   llvm::BitVector DefRegisters; // The union of the aliased def registers.
   llvm::BitVector UseRegisters; // The union of the aliased use registers.
 };
 
 // An instance of an Instruction holding values for each of its Variables.
 struct InstructionInstance {
   InstructionInstance(const Instruction &Instr);
 
+  // No copy.
+  InstructionInstance(const InstructionInstance &) = delete;
+  InstructionInstance &operator=(const InstructionInstance &) = delete;
+
+  // Moving is OK.
+  InstructionInstance(InstructionInstance &&) = default;
+  InstructionInstance &operator=(InstructionInstance &&) = default;
+
+  unsigned getOpcode() const;
   llvm::MCOperand &getValueFor(const Variable &Var);
   llvm::MCOperand &getValueFor(const Operand &Op);
+  bool hasImmediateVariables() const;
 
   // Assigns a Random Value to all Variables that are still Invalid and returns
   // the instance as an llvm::MCInst.
   llvm::MCInst randomizeUnsetVariablesAndBuild();
 
-  const Instruction &Instr;
+  llvm::MCInst randomizeImmediateVariablesAndBuild();
+
+  Instruction Instr;
   llvm::SmallVector<llvm::MCOperand, 4> VariableValues;
 };
 
+// A prototype is a set of InstructionInstances with an explanation of how
+// it's been built. The prototype can then be randomized to exercice several
+// immediate values. It is also used to gather the used registers and define
+// their initial values.
+struct SnippetPrototype {
+  SnippetPrototype() = default;
+
+  // No copy.
+  SnippetPrototype(const SnippetPrototype &) = delete;
+  SnippetPrototype &operator=(const SnippetPrototype &) = delete;
+
+  // Moving is OK.
+  SnippetPrototype(SnippetPrototype &&) = default;
+  SnippetPrototype &operator=(SnippetPrototype &&) = default;
+
+  std::string Explanation;
+  std::vector<InstructionInstance> Snippet;
+};
+
 // Represents the assignment of a Register to an Operand.
 struct RegisterOperandAssignment {
   RegisterOperandAssignment(const Operand *Operand, llvm::MCPhysReg Reg)
       : Op(Operand), Reg(Reg) {}
 
   const Operand *Op; // Pointer to an Explicit Register Operand.
   llvm::MCPhysReg Reg;
 

tools/llvm-exegesis/lib/MCInstrDescView.cpp

 #include <tuple>
 
 #include "llvm/ADT/STLExtras.h"
 
 namespace exegesis {
 
 Instruction::Instruction(const llvm::MCInstrDesc &MCInstrDesc,
                          const RegisterAliasingTrackerCache &RATC)
-    : Description(MCInstrDesc) {
+    : Description(&MCInstrDesc) {
   unsigned OpIndex = 0;
   for (; OpIndex < MCInstrDesc.getNumOperands(); ++OpIndex) {
     const auto &OpInfo = MCInstrDesc.opInfo_begin()[OpIndex];
     Operand Operand;
     Operand.Index = OpIndex;
     Operand.IsDef = (OpIndex < MCInstrDesc.getNumDefs());
     Operand.IsExplicit = true;
     // TODO(gchatelet): Handle isLookupPtrRegClass.
for (auto &Op : Operands)
     }
   // Assigning Variables to tied operands.
   for (auto &Op : Operands)
     if (Op.TiedToIndex >= 0)
       Op.VariableIndex = Operands[Op.TiedToIndex].VariableIndex;
   // Assigning Operands to Variables.
   for (auto &Op : Operands)
     if (Op.VariableIndex >= 0)
-      Variables[Op.VariableIndex].TiedOperands.push_back(&Op);
+      Variables[Op.VariableIndex].TiedOperands.push_back(Op.Index);
   // Processing Aliasing.
   DefRegisters = RATC.emptyRegisters();
   UseRegisters = RATC.emptyRegisters();
   for (const auto &Op : Operands) {
     if (Op.Tracker) {
       auto &Registers = Op.IsDef ? DefRegisters : UseRegisters;
       Registers |= Op.Tracker->aliasedBits();
     }
   }
 }
 
 InstructionInstance::InstructionInstance(const Instruction &Instr)
     : Instr(Instr), VariableValues(Instr.Variables.size()) {}
 
+unsigned InstructionInstance::getOpcode() const {
+  return Instr.Description->getOpcode();
+}
+
 llvm::MCOperand &InstructionInstance::getValueFor(const Variable &Var) {
   return VariableValues[Var.Index];
 }
 
 llvm::MCOperand &InstructionInstance::getValueFor(const Operand &Op) {
   assert(Op.VariableIndex >= 0);
   return getValueFor(Instr.Variables[Op.VariableIndex]);
 }
 
 // forward declaration.
-static void randomize(const Variable &Var, llvm::MCOperand &AssignedValue);
+static void randomize(const Instruction &Instr, const Variable &Var,
+                      llvm::MCOperand &AssignedValue);
+
+bool InstructionInstance::hasImmediateVariables() const {
+  return llvm::any_of(Instr.Variables, [this](const Variable &Var) {
+    assert(!Var.TiedOperands.empty());
+    const unsigned OpIndex = Var.TiedOperands[0];
+    const Operand &Op = Instr.Operands[OpIndex];
+    assert(Op.Info);
+    return Op.Info->OperandType == llvm::MCOI::OPERAND_IMMEDIATE;
+  });
+}
 
 llvm::MCInst InstructionInstance::randomizeUnsetVariablesAndBuild() {
   for (const Variable &Var : Instr.Variables) {
     llvm::MCOperand &AssignedValue = getValueFor(Var);
     if (!AssignedValue.isValid())
-      randomize(Var, AssignedValue);
+      randomize(Instr, Var, AssignedValue);
   }
   llvm::MCInst Result;
-  Result.setOpcode(Instr.Description.Opcode);
+  Result.setOpcode(Instr.Description->Opcode);
   for (const auto &Op : Instr.Operands)
     if (Op.IsExplicit)
       Result.addOperand(getValueFor(Op));
   return Result;
 }
 
+llvm::MCInst InstructionInstance::randomizeImmediateVariablesAndBuild() {
+  return {};
+}
+
 bool RegisterOperandAssignment::
 operator==(const RegisterOperandAssignment &Other) const {
   return std::tie(Op, Reg) == std::tie(Other.Op, Other.Reg);
 }
 
 bool AliasingRegisterOperands::
 operator==(const AliasingRegisterOperands &Other) const {
   return std::tie(Defs, Uses) == std::tie(Other.Defs, Other.Uses);
static size_t randomIndex(size_t Size) {
   return Distribution(randomGenerator());
 }
 
 template <typename C>
 static auto randomElement(const C &Container) -> decltype(Container[0]) {
   return Container[randomIndex(Container.size())];
 }
 
-static void randomize(const Variable &Var, llvm::MCOperand &AssignedValue) {
+static void randomize(const Instruction &Instr, const Variable &Var,
+                      llvm::MCOperand &AssignedValue) {
   assert(!Var.TiedOperands.empty());
-  assert(Var.TiedOperands.front() != nullptr);
-  const Operand &Op = *Var.TiedOperands.front();
+  const Operand &Op = Instr.Operands[Var.TiedOperands.front()];
   assert(Op.Info != nullptr);
   const auto &OpInfo = *Op.Info;
   switch (OpInfo.OperandType) {
   case llvm::MCOI::OperandType::OPERAND_IMMEDIATE:
     // FIXME: explore immediate values too.
     AssignedValue = llvm::MCOperand::createImm(1);
     break;
   case llvm::MCOI::OperandType::OPERAND_REGISTER: {

tools/llvm-exegesis/lib/Uops.h

 
 namespace exegesis {
 
 class UopsBenchmarkRunner : public BenchmarkRunner {
 public:
   using BenchmarkRunner::BenchmarkRunner;
   ~UopsBenchmarkRunner() override;
 
-  llvm::Expected<BenchmarkConfiguration>
-  generateConfiguration(unsigned Opcode) const;
+  llvm::Expected<SnippetPrototype>
+  generatePrototype(unsigned Opcode) const override;
 
 private:
   llvm::Error isInfeasible(const llvm::MCInstrDesc &MCInstrDesc) const;
 
   InstructionBenchmark::ModeE getMode() const override;
 
-  llvm::Expected<std::vector<BenchmarkConfiguration>>
-  createConfigurations(unsigned Opcode) const override;
-
   std::vector<BenchmarkMeasure>
   runMeasurements(const ExecutableFunction &EF,
                   const unsigned NumRepetitions) const override;
 };
 
 } // namespace exegesis
 
 #endif // LLVM_TOOLS_LLVM_EXEGESIS_UOPS_H

tools/llvm-exegesis/lib/Uops.cpp

return llvm::make_error<BenchmarkFailure>(
         "Infeasible : has unknown operands");
   if (llvm::any_of(MCInstrDesc.operands(), hasMemoryOperand))
     return llvm::make_error<BenchmarkFailure>(
         "Infeasible : has memory operands");
   return llvm::Error::success();
 }
 
 // Returns whether this Variable ties Use and Def operands together.
-static bool hasTiedOperands(const Variable &Var) {
+static bool hasTiedOperands(const Instruction &Instr, const Variable &Var) {
   bool HasUse = false;
   bool HasDef = false;
-  for (const Operand *Op : Var.TiedOperands) {
-    if (Op->IsDef)
+  for (const unsigned OpIndex : Var.TiedOperands) {
+    const Operand &Op = Instr.Operands[OpIndex];
+    if (Op.IsDef)
       HasDef = true;
     else
       HasUse = true;
   }
   return HasUse && HasDef;
 }
 
 static llvm::SmallVector<const Variable *, 8>
 getTiedVariables(const Instruction &Instr) {
   llvm::SmallVector<const Variable *, 8> Result;
   for (const auto &Var : Instr.Variables)
-    if (hasTiedOperands(Var))
+    if (hasTiedOperands(Instr, Var))
       Result.push_back(&Var);
   return Result;
 }
 
 static void remove(llvm::BitVector &a, const llvm::BitVector &b) {
   assert(a.size() == b.size());
   for (auto I : b.set_bits())
     a.reset(I);
 }
 
 UopsBenchmarkRunner::~UopsBenchmarkRunner() = default;
 
 InstructionBenchmark::ModeE UopsBenchmarkRunner::getMode() const {
   return InstructionBenchmark::Uops;
 }
 
-llvm::Expected<BenchmarkConfiguration>
-UopsBenchmarkRunner::generateConfiguration(unsigned Opcode) const {
+llvm::Expected<SnippetPrototype>
+UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const {
   const auto &InstrDesc = MCInstrInfo.get(Opcode);
   if (auto E = isInfeasible(InstrDesc))
     return std::move(E);
   const Instruction Instr(InstrDesc, RATC);
   const AliasingConfigurations SelfAliasing(Instr, Instr);
   if (SelfAliasing.empty()) {
-    InstructionInstance II(Instr);
-    BenchmarkConfiguration Conf;
-    Conf.Info = "instruction is parallel, repeating a random one.";
-    Conf.Snippet = {II.randomizeUnsetVariablesAndBuild()};
-    return Conf;
+    SnippetPrototype Prototype;
+    Prototype.Explanation = "instruction is parallel, repeating a random one.";
+    Prototype.Snippet.emplace_back(Instr);
+    return Prototype;
   }
   if (SelfAliasing.hasImplicitAliasing()) {
-    InstructionInstance II(Instr);
-    BenchmarkConfiguration Conf;
-    Conf.Info = "instruction is serial, repeating a random one.";
-    Conf.Snippet = {II.randomizeUnsetVariablesAndBuild()};
-    return Conf;
+    SnippetPrototype Prototype;
+    Prototype.Explanation = "instruction is serial, repeating a random one.";
+    Prototype.Snippet.emplace_back(Instr);
+    return Prototype;
   }
   const auto TiedVariables = getTiedVariables(Instr);
   if (!TiedVariables.empty()) {
     if (TiedVariables.size() > 1)
       return llvm::make_error<llvm::StringError>(
           "Infeasible : don't know how to handle several tied variables",
           llvm::inconvertibleErrorCode());
-    BenchmarkConfiguration Conf;
-    Conf.Info = "instruction has tied variables using static renaming.";
     const Variable *Var = TiedVariables.front();
     assert(Var);
     assert(!Var->TiedOperands.empty());
-    const Operand &Operand = *Var->TiedOperands.front();
-    assert(Operand.Tracker);
-    for (const llvm::MCPhysReg Reg : Operand.Tracker->sourceBits().set_bits()) {
-      InstructionInstance II(Instr);
-      II.getValueFor(*Var) = llvm::MCOperand::createReg(Reg);
-      Conf.Snippet.push_back(II.randomizeUnsetVariablesAndBuild());
+    const Operand &Op = Instr.Operands[Var->TiedOperands.front()];
+    assert(Op.Tracker);
+    SnippetPrototype Prototype;
+    Prototype.Explanation =
+        "instruction has tied variables using static renaming.";
+    for (const llvm::MCPhysReg Reg : Op.Tracker->sourceBits().set_bits()) {
+      Prototype.Snippet.emplace_back(Instr);
+      Prototype.Snippet.back().getValueFor(*Var) =
+          llvm::MCOperand::createReg(Reg);
     }
-    return Conf;
+    return Prototype;
   }
   InstructionInstance II(Instr);
   // No tied variables, we pick random values for defs.
   llvm::BitVector Defs(MCRegisterInfo.getNumRegs());
   for (const auto &Op : Instr.Operands) {
     if (Op.Tracker && Op.IsExplicit && Op.IsDef) {
       auto PossibleRegisters = Op.Tracker->sourceBits();
       remove(PossibleRegisters, RATC.reservedRegisters());
if (Op.Tracker && Op.IsExplicit && !Op.IsDef) {
       auto PossibleRegisters = Op.Tracker->sourceBits();
       remove(PossibleRegisters, RATC.reservedRegisters());
       remove(PossibleRegisters, DefAliases);
       assert(PossibleRegisters.any() && "No register left to choose from");
       const auto RandomReg = randomBit(PossibleRegisters);
       II.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
     }
   }
-  BenchmarkConfiguration Conf;
-  Conf.Info =
+  SnippetPrototype Prototype;
+  Prototype.Explanation =
       "instruction has no tied variables picking Uses different from defs";
-  Conf.Snippet = {II.randomizeUnsetVariablesAndBuild()};
-  return Conf;
-}
-
-llvm::Expected<std::vector<BenchmarkConfiguration>>
-UopsBenchmarkRunner::createConfigurations(unsigned Opcode) const {
-  if (auto E = generateConfiguration(Opcode))
-    return std::vector<BenchmarkConfiguration>{E.get()};
-  else
-    return E.takeError();
+  Prototype.Snippet.push_back(std::move(II));
+  return Prototype;
 }
 
 std::vector<BenchmarkMeasure>
 UopsBenchmarkRunner::runMeasurements(const ExecutableFunction &Function,
                                      const unsigned NumRepetitions) const {
   const auto &SchedModel = State.getSubtargetInfo().getSchedModel();
 
   std::vector<BenchmarkMeasure> Result;

unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

 #include "Uops.h"
 #include "X86InstrInfo.h"
 
 #include <unordered_set>
 
 namespace exegesis {
 namespace {
 
+using testing::HasSubstr;
+using testing::Not;
+using testing::SizeIs;
+
+MATCHER(IsInvalid, "") { return !arg.isValid(); }
+MATCHER(IsReg, "") { return arg.isReg(); }
+
 class X86SnippetGeneratorTest : public ::testing::Test {
 protected:
   X86SnippetGeneratorTest()
       : State("x86_64-unknown-linux", "haswell"),
         MCInstrInfo(State.getInstrInfo()), MCRegisterInfo(State.getRegInfo()) {}
 
   static void SetUpTestCase() {
     LLVMInitializeX86TargetInfo();
     LLVMInitializeX86TargetMC();
     LLVMInitializeX86Target();
     LLVMInitializeX86AsmPrinter();
   }
 
   const LLVMState State;
   const llvm::MCInstrInfo &MCInstrInfo;
   const llvm::MCRegisterInfo &MCRegisterInfo;
 };
 
-class LatencySnippetGeneratorTest : public X86SnippetGeneratorTest {
+template <typename BenchmarkRunner>
+class SnippetGeneratorTest : public X86SnippetGeneratorTest {
 protected:
-  LatencySnippetGeneratorTest() : Runner(State) {}
+  SnippetGeneratorTest() : Runner(State) {}
 
-  BenchmarkConfiguration checkAndGetConfiguration(unsigned Opcode) {
+  SnippetPrototype checkAndGetConfigurations(unsigned Opcode) {
     randomGenerator().seed(0); // Initialize seed.
-    auto ConfOrError = Runner.generateConfiguration(Opcode);
-    EXPECT_FALSE(ConfOrError.takeError()); // Valid configuration.
-    return ConfOrError.get();
+    auto ProtoOrError = Runner.generatePrototype(Opcode);
+    EXPECT_FALSE(ProtoOrError.takeError()); // Valid configuration.
+    return std::move(ProtoOrError.get());
   }
 
-  LatencyBenchmarkRunner Runner;
+  BenchmarkRunner Runner;
 };
 
+using LatencySnippetGeneratorTest =
+    SnippetGeneratorTest<LatencyBenchmarkRunner>;
+
+using UopsSnippetGeneratorTest = SnippetGeneratorTest<UopsBenchmarkRunner>;
+
 TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependency) {
   // ADC16i16 self alias because of implicit use and def.
 
   // explicit use 0       : imm
   // implicit def         : AX
   // implicit def         : EFLAGS
   // implicit use         : AX
   // implicit use         : EFLAGS
   const unsigned Opcode = llvm::X86::ADC16i16;
-  auto Conf = checkAndGetConfiguration(Opcode);
-  EXPECT_THAT(Conf.Info, testing::HasSubstr("implicit"));
-  ASSERT_THAT(Conf.Snippet, testing::SizeIs(1));
-  const llvm::MCInst Instr = Conf.Snippet[0];
-  EXPECT_THAT(Instr.getOpcode(), Opcode);
-  EXPECT_THAT(Instr.getNumOperands(), 1);
-  EXPECT_TRUE(Instr.getOperand(0).isImm()); // Use
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::AX);
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[1], llvm::X86::EFLAGS);
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitUses()[0], llvm::X86::AX);
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitUses()[1], llvm::X86::EFLAGS);
+  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
+  EXPECT_THAT(Proto.Explanation, HasSubstr("implicit"));
+  ASSERT_THAT(Proto.Snippet, SizeIs(1));
+  const InstructionInstance &II = Proto.Snippet[0];
+  EXPECT_THAT(II.getOpcode(), Opcode);
+  ASSERT_THAT(II.VariableValues, SizeIs(1)); // Imm.
+  EXPECT_THAT(II.VariableValues[0], IsInvalid()) << "Immediate is not set";
 }
 
 TEST_F(LatencySnippetGeneratorTest, ExplicitSelfDependency) {
   // ADD16ri self alias because Op0 and Op1 are tied together.
 
   // explicit def 0       : reg RegClass=GR16
   // explicit use 1       : reg RegClass=GR16 | TIED_TO:0
   // explicit use 2       : imm
   // implicit def         : EFLAGS
   const unsigned Opcode = llvm::X86::ADD16ri;
-  auto Conf = checkAndGetConfiguration(Opcode);
-  EXPECT_THAT(Conf.Info, testing::HasSubstr("explicit"));
-  ASSERT_THAT(Conf.Snippet, testing::SizeIs(1));
-  const llvm::MCInst Instr = Conf.Snippet[0];
-  EXPECT_THAT(Instr.getOpcode(), Opcode);
-  EXPECT_THAT(Instr.getNumOperands(), 3);
-  EXPECT_TRUE(Instr.getOperand(0).isReg());
-  EXPECT_TRUE(Instr.getOperand(1).isReg());
-  EXPECT_THAT(Instr.getOperand(0).getReg(), Instr.getOperand(1).getReg())
-      << "Op0 and Op1 should have the same value";
-  EXPECT_TRUE(Instr.getOperand(2).isImm());
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::EFLAGS);
+  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
+  EXPECT_THAT(Proto.Explanation, HasSubstr("explicit"));
+  ASSERT_THAT(Proto.Snippet, SizeIs(1));
+  const InstructionInstance &II = Proto.Snippet[0];
+  EXPECT_THAT(II.getOpcode(), Opcode);
+  ASSERT_THAT(II.VariableValues, SizeIs(2));
+  EXPECT_THAT(II.VariableValues[0], IsReg()) << "Operand 0 and 1";
+  EXPECT_THAT(II.VariableValues[1], IsInvalid()) << "Operand 2 is not set";
 }
 
 TEST_F(LatencySnippetGeneratorTest, DependencyThroughOtherOpcode) {
   // CMP64rr
   // explicit use 0       : reg RegClass=GR64
   // explicit use 1       : reg RegClass=GR64
   // implicit def         : EFLAGS
 
   const unsigned Opcode = llvm::X86::CMP64rr;
-  auto Conf = checkAndGetConfiguration(Opcode);
-  EXPECT_THAT(Conf.Info, testing::HasSubstr("cycle through"));
-  ASSERT_THAT(Conf.Snippet, testing::SizeIs(2));
-  const llvm::MCInst Instr = Conf.Snippet[0];
-  EXPECT_THAT(Instr.getOpcode(), Opcode);
+  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
+  EXPECT_THAT(Proto.Explanation, HasSubstr("cycle through"));
+  ASSERT_THAT(Proto.Snippet, SizeIs(2));
+  const InstructionInstance &II = Proto.Snippet[0];
+  EXPECT_THAT(II.getOpcode(), Opcode);
+  ASSERT_THAT(II.VariableValues, SizeIs(2));
+  EXPECT_THAT(II.VariableValues[0], IsReg());
+  EXPECT_THAT(II.VariableValues[1], IsInvalid());
+  EXPECT_THAT(Proto.Snippet[1].getOpcode(), Not(Opcode));
   // TODO: check that the two instructions alias each other.
 }
 
 TEST_F(LatencySnippetGeneratorTest, LAHF) {
   const unsigned Opcode = llvm::X86::LAHF;
-  auto Conf = checkAndGetConfiguration(Opcode);
-  EXPECT_THAT(Conf.Info, testing::HasSubstr("cycle through"));
-  ASSERT_THAT(Conf.Snippet, testing::SizeIs(2));
-  const llvm::MCInst Instr = Conf.Snippet[0];
-  EXPECT_THAT(Instr.getOpcode(), Opcode);
-}
-
-class UopsSnippetGeneratorTest : public X86SnippetGeneratorTest {
-protected:
-  UopsSnippetGeneratorTest() : Runner(State) {}
-
-  BenchmarkConfiguration checkAndGetConfiguration(unsigned Opcode) {
-    randomGenerator().seed(0); // Initialize seed.
-    auto ConfOrError = Runner.generateConfiguration(Opcode);
-    EXPECT_FALSE(ConfOrError.takeError()); // Valid configuration.
-    return ConfOrError.get();
-  }
+  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
+  EXPECT_THAT(Proto.Explanation, HasSubstr("cycle through"));
+  ASSERT_THAT(Proto.Snippet, SizeIs(2));
+  const InstructionInstance &II = Proto.Snippet[0];
+  EXPECT_THAT(II.getOpcode(), Opcode);
+  ASSERT_THAT(II.VariableValues, SizeIs(0));
 
-  UopsBenchmarkRunner Runner;
-};
-
 TEST_F(UopsSnippetGeneratorTest, ParallelInstruction) {
-  // BNDCL32rr is parallelno matter what.
+  // BNDCL32rr is parallel no matter what.
 
   // explicit use 0       : reg RegClass=BNDR
   // explicit use 1       : reg RegClass=GR32
 
   const unsigned Opcode = llvm::X86::BNDCL32rr;
-  auto Conf = checkAndGetConfiguration(Opcode);
-  EXPECT_THAT(Conf.Info, testing::HasSubstr("parallel"));
-  ASSERT_THAT(Conf.Snippet, testing::SizeIs(1));
-  const llvm::MCInst Instr = Conf.Snippet[0];
-  EXPECT_THAT(Instr.getOpcode(), Opcode);
+  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
+  EXPECT_THAT(Proto.Explanation, HasSubstr("parallel"));
+  ASSERT_THAT(Proto.Snippet, SizeIs(1));
+  const InstructionInstance &II = Proto.Snippet[0];
+  EXPECT_THAT(II.getOpcode(), Opcode);
+  ASSERT_THAT(II.VariableValues, SizeIs(2));
+  EXPECT_THAT(II.VariableValues[0], IsInvalid());
+  EXPECT_THAT(II.VariableValues[1], IsInvalid());
 }
 
 TEST_F(UopsSnippetGeneratorTest, SerialInstruction) {
   // CDQ is serial no matter what.
 
   // implicit def         : EAX
   // implicit def         : EDX
   // implicit use         : EAX
   const unsigned Opcode = llvm::X86::CDQ;
-  auto Conf = checkAndGetConfiguration(Opcode);
-  EXPECT_THAT(Conf.Info, testing::HasSubstr("serial"));
-  ASSERT_THAT(Conf.Snippet, testing::SizeIs(1));
-  const llvm::MCInst Instr = Conf.Snippet[0];
-  EXPECT_THAT(Instr.getOpcode(), Opcode);
+  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
+  EXPECT_THAT(Proto.Explanation, HasSubstr("serial"));
+  ASSERT_THAT(Proto.Snippet, SizeIs(1));
+  const InstructionInstance &II = Proto.Snippet[0];
+  EXPECT_THAT(II.getOpcode(), Opcode);
+  ASSERT_THAT(II.VariableValues, SizeIs(0));
 }
 
 TEST_F(UopsSnippetGeneratorTest, StaticRenaming) {
   // CMOVA32rr has tied variables, we enumarate the possible values to execute
   // as many in parallel as possible.
 
   // explicit def 0       : reg RegClass=GR32
   // explicit use 1       : reg RegClass=GR32 | TIED_TO:0
   // explicit use 2       : reg RegClass=GR32
   // implicit use         : EFLAGS
   const unsigned Opcode = llvm::X86::CMOVA32rr;
-  auto Conf = checkAndGetConfiguration(Opcode);
-  EXPECT_THAT(Conf.Info, testing::HasSubstr("static renaming"));
+  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
+  EXPECT_THAT(Proto.Explanation, HasSubstr("static renaming"));
   constexpr const unsigned kInstructionCount = 15;
-  ASSERT_THAT(Conf.Snippet, testing::SizeIs(kInstructionCount));
+  ASSERT_THAT(Proto.Snippet, SizeIs(kInstructionCount));
   std::unordered_set<unsigned> AllDefRegisters;
-  for (const auto &Inst : Conf.Snippet)
-    AllDefRegisters.insert(Inst.getOperand(0).getReg());
-  EXPECT_THAT(AllDefRegisters, testing::SizeIs(kInstructionCount))
+  for (const auto &II : Proto.Snippet) {
+    ASSERT_THAT(II.VariableValues, SizeIs(2));
+    AllDefRegisters.insert(II.VariableValues[0].getReg());
+  }
+  EXPECT_THAT(AllDefRegisters, SizeIs(kInstructionCount))
       << "Each instruction writes to a different register";
 }
 
 TEST_F(UopsSnippetGeneratorTest, NoTiedVariables) {
   // CMOV_GR32 has no tied variables, we make sure def and use are different
   // from each other.
 
   // explicit def 0       : reg RegClass=GR32
   // explicit use 1       : reg RegClass=GR32
   // explicit use 2       : reg RegClass=GR32
   // explicit use 3       : imm
   // implicit use         : EFLAGS
   const unsigned Opcode = llvm::X86::CMOV_GR32;
-  auto Conf = checkAndGetConfiguration(Opcode);
-  EXPECT_THAT(Conf.Info, testing::HasSubstr("no tied variables"));
-  ASSERT_THAT(Conf.Snippet, testing::SizeIs(1));
-  const llvm::MCInst Instr = Conf.Snippet[0];
-  EXPECT_THAT(Instr.getOpcode(), Opcode);
-  EXPECT_THAT(Instr.getNumOperands(), 4);
-  EXPECT_THAT(Instr.getOperand(0).getReg(),
-              testing::Not(Instr.getOperand(1).getReg()))
+  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
+  EXPECT_THAT(Proto.Explanation, HasSubstr("no tied variables"));
+  ASSERT_THAT(Proto.Snippet, SizeIs(1));
+  const InstructionInstance &II = Proto.Snippet[0];
+  EXPECT_THAT(II.getOpcode(), Opcode);
+  ASSERT_THAT(II.VariableValues, SizeIs(4));
+  EXPECT_THAT(II.VariableValues[0].getReg(), Not(II.VariableValues[1].getReg()))
       << "Def is different from first Use";
-  EXPECT_THAT(Instr.getOperand(0).getReg(),
-              testing::Not(Instr.getOperand(2).getReg()))
+  EXPECT_THAT(II.VariableValues[0].getReg(), Not(II.VariableValues[2].getReg()))
       << "Def is different from second Use";
-  EXPECT_THAT(Instr.getOperand(3).getImm(), 1);
+  EXPECT_THAT(II.VariableValues[3], IsInvalid());
 }
 
 } // namespace
 } // namespace exegesis