[MCA][x86][NFC] Add tests for -register-file-stats, -scheduler-stats

[lebedev.ri]

Summary

There does not seem to be any other tests for this.
Split off from D47676.

[RKSimon]

test/tools/llvm-mca/X86/register-file-statistics.s

4 ↗

(On Diff #151407)

Try to use shorter prefixes: SNB, IVB, HSW, BDW are the most common acronyms

11 ↗

(On Diff #151407)

Use --check-prefixes if you can, although I don't see any usage of ALL.

45 ↗

(On Diff #151407)

A lot of these prefixes look redundant?

[lebedev.ri]

test/tools/llvm-mca/X86/register-file-statistics.s

45 ↗

(On Diff #151407)

Oh, indeed.

BTW, in this file, everything before Register File statistics: isn't expected to be here.
Can

Iterations:        100
Instructions:      100
Total Cycles:      51
Dispatch Width:    2
IPC:               1.96
Block RThroughput: 0.5

be named a "-basic-stats", and an option to control that output be added?
@andreadb does that sound reasonable?

[lebedev.ri]

Remove leftover noise.

[andreadb]

test/tools/llvm-mca/X86/register-file-statistics.s

45 ↗

(On Diff #151407)

Not really.
I think the summary view should never be optional in llvm-mca.
It is only a few lines, and it gives a nice overview of the run.

[lebedev.ri]

test/tools/llvm-mca/X86/register-file-statistics.s

45 ↗

(On Diff #151407)

I agree that it is quite essential for normal usage,
but in the edge-case use-case like this, it does not seem to be of much use..

test/tools/llvm-mca/X86/scheduler-queue-usage.s

110–114 ↗

(On Diff #151464)

Hm, it seems i have picked a bad example.

[lebedev.ri]

Use xor %eax, %ebx instead of xor %eax, %eax
so that btver2 also shows up in -scheduler-stats

[andreadb]

test/tools/llvm-mca/X86/register-file-statistics.s

45 ↗

(On Diff #151407)

My opinion is that register pressure should be always put into perspective.
Register pressure tends to change over the course of a simulation for many reasons (i.e. the presence of long latency instructions, long data dependencies, lack of resources versus high dispatch rate). So, the number of iterations usually matters, and it helps putting the register usage into perspective.
That being said, if other reviewers are okay with this change, then I won't oppose it.

[lebedev.ri]

test/tools/llvm-mca/X86/register-file-statistics.s

45 ↗

(On Diff #151407)

I'm not denying any of that.
I'm simply saying that in these two testcases, the only thing they are intended to produce,
is to dump the ProcResGroup<>.BufferSize, and RegisterFile<>.NumPhysRegs.

[andreadb]

test/tools/llvm-mca/X86/register-file-statistics.s

45 ↗

(On Diff #151407)

As I wrote, I am okay with this change if other reviewers are okay with it.
Since Clement (and presumably Greg) are okay with it (based on the feedback from D48209), then I am not going to oppose this patch.

As a side note, the subject of this patch is a bit misleading.
There are already existing tests for -register-file-stats and -scheduler-stats in X86/BtVer2 directory.

My understanding is that your original plan is to add test coverage specifically for the register file usage in Znver1 (in the summary, you wrote that this is a spin-off of D47676). If my understanding is correct, then please move these tests into directory ZnVer1, and make those tests znver1 only.

[lebedev.ri]

test/tools/llvm-mca/X86/register-file-statistics.s

45 ↗

(On Diff #151407)

Thanks!

...

Yes and no.
It was indeed intended to show the Znver1 change.
But it tries to address somewhat larger problem that these basic, common to all processors,
things aren't being tested for all the processors.
I.e. much like the test/tools/llvm-mca/X86/cpus.s, which is catch-all.

So i could make it znver1-specific, but it seems that in this case,
the more general approach is slightly better.
It would of course not make much sense to do that for every asm sequence
(as opposed to duplicating those test files per-cpu).

[andreadb]

Well, I guess it doesn't hurt to have these new tests.
We already have tests for all the views and all the stats. But you are right, we don't have tests _only_ for those two flags.

It looks good to me.

Thanks,
-Andrea

[lebedev.ri]

In D48190#1133508, @andreadb wrote:

Well, I guess it doesn't hurt to have these new tests.
We already have tests for all the views and all the stats. But you are right, we don't have tests _only_ for those two flags.

It looks good to me.

Thanks,
-Andrea

Thank you for the review!

llvm/trunk/test/tools/llvm-mca/X86/register-file-statistics.s

+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,BTVER2 %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,ZNVER1 %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,SNB %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=ivybridge -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,IVB %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,HSW %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=broadwell -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,BDW %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=knl -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,KNL %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=skylake -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,SKX %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,SKX-AVX512 %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=slm -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,SLM %s
+
+xor %eax, %ebx
+
+# ALL:             Iterations:        1
+# ALL-NEXT:        Instructions:      1
+# ALL-NEXT:        Total Cycles:      4
+
+# BDW-NEXT:        Dispatch Width:    4
+# BTVER2-NEXT:     Dispatch Width:    2
+# HSW-NEXT:        Dispatch Width:    4
+# IVB-NEXT:        Dispatch Width:    4
+# KNL-NEXT:        Dispatch Width:    4
+# SKX-NEXT:        Dispatch Width:    6
+# SKX-AVX512-NEXT: Dispatch Width:    6
+# SLM-NEXT:        Dispatch Width:    2
+# SNB-NEXT:        Dispatch Width:    4
+# ZNVER1-NEXT:     Dispatch Width:    4
+
+# ALL-NEXT:        IPC:               0.25
+
+# BDW-NEXT:        Block RThroughput: 0.3
+# BTVER2-NEXT:     Block RThroughput: 0.5
+# HSW-NEXT:        Block RThroughput: 0.3
+# IVB-NEXT:        Block RThroughput: 0.3
+# KNL-NEXT:        Block RThroughput: 0.3
+# SKX-NEXT:        Block RThroughput: 0.3
+# SKX-AVX512-NEXT: Block RThroughput: 0.3
+# SLM-NEXT:        Block RThroughput: 0.5
+# SNB-NEXT:        Block RThroughput: 0.3
+# ZNVER1-NEXT:     Block RThroughput: 0.3
+
+# ALL:             Register File statistics:
+# ALL-NEXT:        Total number of mappings created:    2
+# ALL-NEXT:        Max number of mappings used:         2
+
+# BTVER2:          *  Register File #1 -- JFpuPRF:
+# BTVER2-NEXT:        Number of physical registers:     72
+# BTVER2-NEXT:        Total number of mappings created: 0
+# BTVER2-NEXT:        Max number of mappings used:      0
+
+# BTVER2:          *  Register File #2 -- JIntegerPRF:
+# BTVER2-NEXT:        Number of physical registers:     64
+# BTVER2-NEXT:        Total number of mappings created: 2
+# BTVER2-NEXT:        Max number of mappings used:      2

llvm/trunk/test/tools/llvm-mca/X86/scheduler-queue-usage.s

+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BTVER2 %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,ZNVER1 %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,SNB %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=ivybridge -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,IVB %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,HSW %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=broadwell -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BDW %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=knl -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,KNL %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=skylake -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,SKX %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,SKX-AVX512 %s
+# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=slm -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,SLM %s
+
+xor %eax, %ebx
+
+# ALL:             Iterations:        1
+# ALL-NEXT:        Instructions:      1
+# ALL-NEXT:        Total Cycles:      4
+
+# BDW-NEXT:        Dispatch Width:    4
+# BTVER2-NEXT:     Dispatch Width:    2
+# HSW-NEXT:        Dispatch Width:    4
+# IVB-NEXT:        Dispatch Width:    4
+# KNL-NEXT:        Dispatch Width:    4
+# SKX-NEXT:        Dispatch Width:    6
+# SKX-AVX512-NEXT: Dispatch Width:    6
+# SLM-NEXT:        Dispatch Width:    2
+# SNB-NEXT:        Dispatch Width:    4
+# ZNVER1-NEXT:     Dispatch Width:    4
+
+# ALL-NEXT:        IPC:               0.25
+
+# BDW-NEXT:        Block RThroughput: 0.3
+# BTVER2-NEXT:     Block RThroughput: 0.5
+# HSW-NEXT:        Block RThroughput: 0.3
+# IVB-NEXT:        Block RThroughput: 0.3
+# KNL-NEXT:        Block RThroughput: 0.3
+# SKX-NEXT:        Block RThroughput: 0.3
+# SKX-AVX512-NEXT: Block RThroughput: 0.3
+# SLM-NEXT:        Block RThroughput: 0.5
+# SNB-NEXT:        Block RThroughput: 0.3
+# ZNVER1-NEXT:     Block RThroughput: 0.3
+
+# ALL:             Schedulers - number of cycles where we saw N instructions issued:
+# ALL-NEXT:        [# issued], [# cycles]
+# ALL-NEXT:         0,          3  (75.0%)
+# ALL-NEXT:         1,          1  (25.0%)
+
+# BDW:             Scheduler's queue usage:
+# BDW-NEXT:        BWPortAny,  1/60
+
+# HSW:             Scheduler's queue usage:
+# HSW-NEXT:        HWPortAny,  1/60
+
+# KNL:             Scheduler's queue usage:
+# KNL-NEXT:        HWPortAny,  1/60
+
+# BTVER2:          Scheduler's queue usage:
+# BTVER2-NEXT:     JALU01,  1/20
+# BTVER2-NEXT:     JFPU01,  0/18
+# BTVER2-NEXT:     JLSAGU,  0/12
+
+# SLM:             Scheduler's queue usage:
+# SLM-NEXT:        No scheduler resources used.
+
+# IVB:             Scheduler's queue usage:
+# IVB-NEXT:        SBPortAny,  1/54
+
+# SNB:             Scheduler's queue usage:
+# SNB-NEXT:        SBPortAny,  1/54
+
+# SKX:             Scheduler's queue usage:
+# SKX-NEXT:        SKLPortAny,  1/60
+
+# SKX-AVX512:      Scheduler's queue usage:
+# SKX-AVX512-NEXT: SKXPortAny,  1/60
+
+# ZNVER1:          Scheduler's queue usage:
+# ZNVER1-NEXT:     ZnAGU,  0/28
+# ZNVER1-NEXT:     ZnALU,  1/56