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Differential D48133

[AMDGPU] Corrected computeKnownBits for V_PERM_B32
ClosedPublic

Authored by rampitec on Jun 13 2018, 9:30 AM.

Details

Reviewers
msearles
Commits
rG7bec57300c79: [AMDGPU] Corrected computeKnownBits for V_PERM_B32
rL334640: [AMDGPU] Corrected computeKnownBits for V_PERM_B32

Diff Detail

Repository
rL LLVM

Event Timeline

rampitec created this revision.Jun 13 2018, 9:30 AM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptJun 13 2018, 9:30 AM
msearles accepted this revision.Jun 13 2018, 9:52 AM

LGTM

This revision is now accepted and ready to land.Jun 13 2018, 9:52 AM
Closed by commit rL334640: [AMDGPU] Corrected computeKnownBits for V_PERM_B32 (authored by rampitec). · Explain WhyJun 13 2018, 11:57 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
15 lines
test/
CodeGen/
AMDGPU/
22 lines

Diff 151219

llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 4,311 Lines • ▼ Show 20 Lines if (!CMask)
return; return;
KnownBits LHSKnown, RHSKnown; KnownBits LHSKnown, RHSKnown;
DAG.computeKnownBits(Op.getOperand(0), LHSKnown, Depth + 1); DAG.computeKnownBits(Op.getOperand(0), LHSKnown, Depth + 1);
DAG.computeKnownBits(Op.getOperand(1), RHSKnown, Depth + 1); DAG.computeKnownBits(Op.getOperand(1), RHSKnown, Depth + 1);
unsigned Sel = CMask->getZExtValue(); unsigned Sel = CMask->getZExtValue();
for (unsigned I = 0; I < 32; I += 8) { for (unsigned I = 0; I < 32; I += 8) {
unsigned ByteMask = 0xff << I;
unsigned SelBits = Sel & 0xff; unsigned SelBits = Sel & 0xff;
if (SelBits < 4) { if (SelBits < 4) {
Known.One |= RHSKnown.One & ByteMask; SelBits *= 8;
Known.Zero |= RHSKnown.Zero & ByteMask; Known.One |= ((RHSKnown.One.getZExtValue() >> SelBits) & 0xff) << I;
Known.Zero |= ((RHSKnown.Zero.getZExtValue() >> SelBits) & 0xff) << I;
} else if (SelBits < 7) { } else if (SelBits < 7) {
Known.One |= LHSKnown.One & ByteMask; SelBits = (SelBits & 3) * 8;
Known.Zero |= LHSKnown.Zero & ByteMask; Known.One |= ((LHSKnown.One.getZExtValue() >> SelBits) & 0xff) << I;
Known.Zero |= ((LHSKnown.Zero.getZExtValue() >> SelBits) & 0xff) << I;
} else if (SelBits == 0x0c) { } else if (SelBits == 0x0c) {
Known.Zero |= ByteMask; Known.Zero |= 0xff << I;
} else if (SelBits > 0x0c) { } else if (SelBits > 0x0c) {
Known.One |= ByteMask; Known.One |= 0xff << I;
} }
Sel >>= 8; Sel >>= 8;
} }
break; break;
} }
case ISD::INTRINSIC_WO_CHAIN: { case ISD::INTRINSIC_WO_CHAIN: {
unsigned IID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); unsigned IID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
switch (IID) { switch (IID) {
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/permute.ll

Show First 20 Lines • Show All 190 Lines • ▼ Show 20 Linesbb:
%tmp4 = or i32 %tmp2, %tmp3 %tmp4 = or i32 %tmp2, %tmp3
%and = and i32 %tmp4, 4278190335 %and = and i32 %tmp4, 4278190335
store i32 %and, i32 addrspace(1)* %gep, align 4 store i32 %and, i32 addrspace(1)* %gep, align 4
%v = and i32 %and, 16776964 %v = and i32 %and, 16776964
store i32 %v, i32 addrspace(1)* %arg, align 4 store i32 %v, i32 addrspace(1)* %arg, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}known_ffff8004:
; GCN-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff0500
; GCN-DAG: v_mov_b32_e32 [[RES:v[0-9]+]], 0xffff8004
; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
define amdgpu_kernel void @known_ffff8004(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
bb:
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
%load = load i32, i32 addrspace(1)* %gep, align 4
%mask1 = or i32 %arg1, 4
%mask2 = or i32 %load, 32768 ; 0x8000
%and = and i32 %mask1, 16711935 ; 0x00ff00ff
%tmp1 = and i32 %mask2, 4294967040 ; 0xffffff00
%tmp2 = or i32 %tmp1, 4294901760 ; 0xffff0000
%tmp3 = or i32 %tmp2, %and
store i32 %tmp3, i32 addrspace(1)* %gep, align 4
%v = and i32 %tmp3, 4294934532 ; 0xffff8004
store i32 %v, i32 addrspace(1)* %arg, align 4
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()