update simplifyUnsignedRangeCheck function's test case.

[HLJ2009]

Summary

For both operands are unsigned, add the following optimization test case.

1. X > Y && X != 0 --> X > Y
2. X > Y || X != 0 --> X != 0
3. X <= Y || X != 0 --> true
4. X <= Y || X == 0 --> X <= Y
5. X > Y && X == 0 --> false

[spatel]

Adding Roman as reviewer - do these tests answer the questions from D47922 about whether the existing transform is miscompiling or just incomplete?

[lebedev.ri]

In D47972#1127515, @spatel wrote:

Adding Roman as reviewer - do these tests answer the questions from D47922 about whether the existing transform is miscompiling or just incomplete?

These tests are valid as per alive.
But i'm not sure, are they on top of git master, or D47922?
Why there is no test output change in D47922?

[lebedev.ri]

@HLJ2009 just in case, let me reiterate:
These tests need to be generated for the svn trunk version of llvm, not D47922.
They should be (when accepted) committed before the dependent revision.
They need to have good coverage, ideally for all the previously-missing cases, and for all the cases that will be affected by the dependent revision. (well, not all, obviously)
Then, D47922 needs to be rebased ontop of this change (and do mark it as a dependent in phabricator, to signify it), and the effect of the code change should be visible in the tests.

test/Transforms/InstSimplify/AndOrXor.ll

;
   %1 = icmp ult i32 %x, %y
   %2 = icmp ne i32 %y, 0
   %3 = and i1 %1, %2
   ret i1 %3
 }
 
 define i1 @and_icmp2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @and_icmp2(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
+;
+  %1 = icmp ugt i32 %x, %y
+  %2 = icmp ne i32 %x, 0
+  %3 = and i1 %1, %2
+  ret i1 %3
+}
+
+define i1 @and_icmp3(i32 %x, i32 %y) {
+; CHECK-LABEL: @and_icmp3(
 ; CHECK-NEXT:    ret i1 false
 ;
   %1 = icmp ult i32 %x, %y
   %2 = icmp eq i32 %y, 0
   %3 = and i1 %1, %2
   ret i1 %3
 }
 
+define i1 @and_icmp4(i32 %x, i32 %y) {
+; CHECK-LABEL: @and_icmp4(
+; CHECK-NEXT:    ret i1 false
+;
+  %1 = icmp ugt i32 %x, %y
+  %2 = icmp eq i32 %x, 0
+  %3 = and i1 %1, %2
+  ret i1 %3
+}
+
 define i1 @or_icmp1(i32 %x, i32 %y) {
 ; CHECK-LABEL: @or_icmp1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %1 = icmp ult i32 %x, %y
   %2 = icmp ne i32 %y, 0
   %3 = or i1 %1, %2
   ret i1 %3
 }
 
 define i1 @or_icmp2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @or_icmp2(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne i32 [[X:%.*]], 0
+; CHECK-NEXT:    ret i1 [[TMP1]]
+;
+  %1 = icmp ugt i32 %x, %y
+  %2 = icmp ne i32 %x, 0
+  %3 = or i1 %1, %2
+  ret i1 %3
+}
+
+define i1 @or_icmp3(i32 %x, i32 %y) {
+; CHECK-LABEL: @or_icmp3(
 ; CHECK-NEXT:    ret i1 true
 ;
   %1 = icmp uge i32 %x, %y
   %2 = icmp ne i32 %y, 0
   %3 = or i1 %1, %2
   ret i1 %3
 }
 
-define i1 @or_icmp3(i32 %x, i32 %y) {
-; CHECK-LABEL: @or_icmp3(
+define i1 @or_icmp4(i32 %x, i32 %y) {
+; CHECK-LABEL: @or_icmp4(
+; CHECK-NEXT:    ret i1 true
+;
+  %1 = icmp ule i32 %x, %y
+  %2 = icmp ne i32 %x, 0
+  %3 = or i1 %1, %2
+  ret i1 %3
+}
+
+define i1 @or_icmp5(i32 %x, i32 %y) {
+; CHECK-LABEL: @or_icmp5(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %1 = icmp uge i32 %x, %y
   %2 = icmp eq i32 %y, 0
   %3 = or i1 %1, %2
   ret i1 %3
 }
 
+define i1 @or_icmp6(i32 %x, i32 %y) {
+; CHECK-LABEL: @or_icmp6(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ule i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[TMP1]]
+;
+  %1 = icmp ule i32 %x, %y
+  %2 = icmp eq i32 %x, 0
+  %3 = or i1 %1, %2
+  ret i1 %3
+}
+
 ; PR27869 - Look through casts to eliminate cmps and bitwise logic.
 
 define i32 @and_of_zexted_icmps(i32 %i) {
 ; CHECK-LABEL: @and_of_zexted_icmps(
 ; CHECK-NEXT:    ret i32 0
 ;
   %cmp0 = icmp eq i32 %i, 0
   %conv0 = zext i1 %cmp0 to i32