[AArch64][SVE] Initial store patterns for SVE

[huntergr]

Summary

Adds simple ISel patterns for stores of legal integer scalable
vector types with a single base address, plus unit tests for same.

Part of the initial SVE codegen series, rfc will be posted soon. Note: this patch is currently just to support the scalable vector codegen rfc, and does not need a full review yet.

[huntergr]

A better set of patterns will be created later.

lib/Target/AArch64/AArch64SVEInstrInfo.td

def : Pat<(nxv16i8 (AArch64seriesvec GPR32:$start, GPR32:$step)),
             (INDEX_RR_B $start, $step)>;
   def : Pat<(nxv8i16 (AArch64seriesvec GPR32:$start, GPR32:$step)),
             (INDEX_RR_H $start, $step)>;
   def : Pat<(nxv4i32 (AArch64seriesvec GPR32:$start, GPR32:$step)),
             (INDEX_RR_S $start, $step)>;
   def : Pat<(nxv2i64 (AArch64seriesvec GPR64:$start, GPR64:$step)),
             (INDEX_RR_D $start, $step)>;
 
+  // Unoptimized stores
+  def : Pat<(store (nxv16i8 ZPR:$val), GPR64sp:$base),
+            (ST1B_IMM ZPR:$val, (PTRUE_B 31), GPR64sp:$base, (i64 0))>;
+  def : Pat<(store (nxv8i16 ZPR:$val), GPR64sp:$base),
+            (ST1H_IMM ZPR:$val, (PTRUE_H 31), GPR64sp:$base, (i64 0))>;
+  def : Pat<(store (nxv4i32 ZPR:$val), GPR64sp:$base),
+            (ST1W_IMM ZPR:$val, (PTRUE_S 31), GPR64sp:$base, (i64 0))>;
+  def : Pat<(store (nxv2i64 ZPR:$val), GPR64sp:$base),
+            (ST1D_IMM ZPR:$val, (PTRUE_D 31), GPR64sp:$base, (i64 0))>;
+
 }

test/CodeGen/AArch64/SVE/st1.ll

+; RUN: llc -verify-machineinstrs -mattr=+sve < %s | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-gnueabi"
+
+
+define void @st1_b(<scalable 16 x i8> %val, <scalable 16 x i8>* %ptr) {
+; CHECK-LABEL: st1_b:
+; CHECK: ptrue [[PG:p[0-9]+]].b
+; CHECK-NEXT: st1b { z0.b }, [[PG]], [x0]
+; CHECK-NEXT: ret
+  store <scalable 16 x i8> %val, <scalable 16 x i8>* %ptr
+  ret void
+}
+
+define void @st1_h(<scalable 8 x i16> %val, <scalable 8 x i16>* %ptr) {
+; CHECK-LABEL: st1_h:
+; CHECK: ptrue [[PG:p[0-9]+]].h
+; CHECK-NEXT: st1h { z0.h }, [[PG]], [x0]
+; CHECK-NEXT: ret
+  store <scalable 8 x i16> %val, <scalable 8 x i16>* %ptr
+  ret void
+}
+
+define void @st1_w(<scalable 4 x i32> %val, <scalable 4 x i32>* %ptr) {
+; CHECK-LABEL: st1_w:
+; CHECK: ptrue [[PG:p[0-9]+]].s
+; CHECK-NEXT: st1w { z0.s }, [[PG]], [x0]
+; CHECK-NEXT: ret
+  store <scalable 4 x i32> %val, <scalable 4 x i32>* %ptr
+  ret void
+}
+
+define void @st1_d(<scalable 2 x i64> %val, <scalable 2 x i64>* %ptr) {
+; CHECK-LABEL: st1_d:
+; CHECK: ptrue [[PG:p[0-9]+]].d
+; CHECK-NEXT: st1d { z0.d }, [[PG]], [x0]
+; CHECK-NEXT: ret
+  store <scalable 2 x i64> %val, <scalable 2 x i64>* %ptr
+  ret void
+}