[SelectionDAG] Provide default expansion for rotates

[kparzysz]

Summary

Implement default legalization of rotates: either in terms of the rotation in the opposite direction (if legal), or in terms of shifts and ors.

Implement generating of rotate instructions for Hexagon. Hexagon only supports rotates by an immediate value, so implement custom lowering of ROTL/ROTR on Hexagon. If a rotate is not legal, use the default expansion.

[efriedma]

Please split ReassociateOrForRotate into a separate patch; it's conceptually separate and likely to affect other targets.

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

3929 ↗

(On Diff #149783)

This lowering is wrong (consider c==0, c==64). Maybe (or (shl x, (and c, w-1), (srl x, (and (sub 0, c), w-1)) instead?

[kparzysz]

Removed the rotation generation from this patch, applied Eli's suggestions.

[RKSimon]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

4985 ↗

(On Diff #149820)

This might be useful as general helper function - add it to the DAGCombiner class for reuse?

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

3912 ↗

(On Diff #149820)

Use OpVT.getScalarSizeInBits() - hopefully we might be able to use this for vector cases as well at some point soon.

3918 ↗

(On Diff #149820)

Move the Sub = DAG.getNode into the if() case? I don't think its used anywhere else.

lib/Target/Hexagon/HexagonISelLowering.cpp

1359 ↗

(On Diff #149820)

Is this relevant to rotation support?

1366 ↗

(On Diff #149820)

Is this relevant to rotation support?

2100 ↗

(On Diff #149820)

I don't think you need the getNode() here

[kparzysz]

lib/Target/Hexagon/HexagonISelLowering.cpp

2100 ↗

(On Diff #149820)

I try to keep the SDValue->SDNode conversions explicit in general.

[kparzysz]

Applied Simon's comments.

[RKSimon]

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

3923 ↗

(On Diff #149968)

Is there any way that we can get here with a bit width that isn't power-of-two? In which case we'd have to adjust this and use UREM not AND........

[kparzysz]

Replaced (and x, w-1) with (urem x, w).

[kparzysz]

Remove incorrect assertion that was added in the previous patch. The version with urem works for non-power-of-2 as well.

[efriedma]

Currently it's impossible to reach LegalizeDAG with an integer that isn't a power of two (only power-of-two integers can be specified as legal types), but I guess it's better to future-proof.

I like to see a test with explicit CHECK lines for the assembly generated using the legalization in SelectionDAGLegalize::ExpandNode, so we'll know if something changes.

[kparzysz]

Turns out the UREM approach has a downside: the UREM is legalized before it gets to the combiner, so on architectures that don't have div/mod, it will be expanded into a libcall. I'm going to change it back to an AND.

The testcase rotate.ll already has a couple of cases where the expansion takes place (f1, f3, f5, and f7), but now it only checks that there was no rotate used. I can add check for the actual assembly.

[kparzysz]

Using UREM ended up calling runtime functions (since UREM is a libcall on Hexagon), so I switched it back to using AND. Eli's comment confirms that only types that are power-of-2 bits wide can exist at this point.

Per Eli's request, expanded the testcase to include checks for the actual expansion code.

[efriedma]

test/CodeGen/Hexagon/rotate.ll

107 ↗

(On Diff #150046)

This looks correct, but low quality. Trunk generates 3 instructions, the ideal rotate expansion would generate 5 instructions (I think), this is 6 instructions.

[kparzysz]

Removed a redundant AND from rotate expansion.

[RKSimon]

LGTM @efriedma any more comments?

[efriedma]

The AND you removed wasn't redundant: 32-0 is 32, not 0.

[efriedma]

(When I said there was a redundant operation, I was referring to the second SUB.)

[kparzysz]

In D47725#1126768, @efriedma wrote:

(When I said there was a redundant operation, I was referring to the second SUB.)

Yeah, the first sub came from ROTR->ROTL conversion, so it was actually 5 instructions for the ROTL alone. I think we should be able to optimize it further on targets where large shift amounts generate 0 (in DAG combiner?).

[kparzysz]

It's now 5 instructions everywhere, and the and is back.

[efriedma]

Hmm... yes, I guess the AND isn't necessary if the shift produces either zero or the input, which is true for every target I can think of. But (SHL x, 32) is defined to produce undef for a 32-bit input, not some target-specific result, so you can't depend on that. Might make sense to add a dedicated target-independent opcode to represent it.

[efriedma]

LGTM

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

private:
     /// Try to transform a truncation where C is a constant:
     ///     (trunc (and X, C)) -> (and (trunc X), (trunc C))
     ///
     /// \p N needs to be a truncation and its first operand an AND. Other
     /// requirements are checked by the function (e.g. that trunc is
     /// single-use) and if missed an empty SDValue is returned.
     SDValue distributeTruncateThroughAnd(SDNode *N);
 
+    /// Helper function to determine whether the target supports operation
+    /// given by \p Opcode for type \p VT, that is, whether the operation
+    /// is legal or custom before legalizing operations, and whether is
+    /// legal (but not custom) after legalization.
+    bool hasOperation(unsigned Opcode, EVT VT) {
+      if (LegalOperations)
+        return TLI.isOperationLegal(Opcode, VT);
+      return TLI.isOperationLegalOrCustom(Opcode, VT);
+    }
+
   public:
     /// Runs the dag combiner on all nodes in the work list
     void Run(CombineLevel AtLevel);
 
     SelectionDAG &getDAG() const { return DAG; }
 
     /// Returns a type large enough to hold any valid shift amount - before type
     /// legalization these can be huge.

 // idioms for rotate, and if the target supports rotation instructions, generate
 // a rot[lr].
 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
   // Must be a legal type.  Expanded 'n promoted things won't work with rotates.
   EVT VT = LHS.getValueType();
   if (!TLI.isTypeLegal(VT)) return nullptr;
 
   // The target must have at least one rotate flavor.
-  bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
-  bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
+  bool HasROTL = hasOperation(ISD::ROTL, VT);
+  bool HasROTR = hasOperation(ISD::ROTR, VT);
   if (!HasROTL && !HasROTR) return nullptr;
 
   // Check for truncated rotate.
   if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE &&
       LHS.getOperand(0).getValueType() == RHS.getOperand(0).getValueType()) {
     assert(LHS.getValueType() == RHS.getValueType());
     if (SDNode *Rot = MatchRotate(LHS.getOperand(0), RHS.getOperand(0), DL)) {
       return DAG.getNode(ISD::TRUNCATE, SDLoc(LHS), LHS.getValueType(),

llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

for (unsigned Idx = 0; Idx < NumElem; Idx++) {
       Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
                                     VT.getScalarType(), Ex, Sh));
     }
 
     SDValue Result = DAG.getBuildVector(Node->getValueType(0), dl, Scalars);
     ReplaceNode(SDValue(Node, 0), Result);
     break;
   }
+  case ISD::ROTL:
+  case ISD::ROTR: {
+    bool IsLeft = Node->getOpcode() == ISD::ROTL;
+    SDValue Op0 = Node->getOperand(0), Op1 = Node->getOperand(1);
+    EVT ResVT = Node->getValueType(0);
+    EVT OpVT = Op0.getValueType();
+    assert(OpVT == ResVT &&
+           "The result and the operand types of rotate should match");
+    EVT ShVT = Op1.getValueType();
+    SDValue Width = DAG.getConstant(OpVT.getScalarSizeInBits(), dl, ShVT);
+
+    // If a rotate in the other direction is legal, use it.
+    unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL;
+    if (TLI.isOperationLegal(RevRot, ResVT)) {
+      SDValue Sub = DAG.getNode(ISD::SUB, dl, ShVT, Width, Op1);
+      Results.push_back(DAG.getNode(RevRot, dl, ResVT, Op0, Sub));
+      break;
+    }
+
+    // Otherwise,
+    //   (rotl x, c) -> (or (shl x, (and c, w-1)), (srl x, (and w-c, w-1)))
+    //   (rotr x, c) -> (or (srl x, (and c, w-1)), (shl x, (and w-c, w-1)))
+    //
+    assert(isPowerOf2_32(OpVT.getScalarSizeInBits()) &&
+           "Expecting the type bitwidth to be a power of 2");
+    unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL;
+    unsigned HsOpc = IsLeft ? ISD::SRL : ISD::SHL;
+    SDValue Width1 = DAG.getNode(ISD::SUB, dl, ShVT,
+                                 Width, DAG.getConstant(1, dl, ShVT));
+    SDValue NegOp1 = DAG.getNode(ISD::SUB, dl, ShVT, Width, Op1);
+    SDValue And0 = DAG.getNode(ISD::AND, dl, ShVT, Op1, Width1);
+    SDValue And1 = DAG.getNode(ISD::AND, dl, ShVT, NegOp1, Width1);
+
+    SDValue Or = DAG.getNode(ISD::OR, dl, ResVT,
+                             DAG.getNode(ShOpc, dl, ResVT, Op0, And0),
+                             DAG.getNode(HsOpc, dl, ResVT, Op0, And1));
+    Results.push_back(Or);
+    break;
+  }
+
   case ISD::GLOBAL_OFFSET_TABLE:
   case ISD::GlobalAddress:
   case ISD::GlobalTLSAddress:
   case ISD::ExternalSymbol:
   case ISD::ConstantPool:
   case ISD::JumpTable:
   case ISD::INTRINSIC_W_CHAIN:
   case ISD::INTRINSIC_WO_CHAIN:

llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h

public:
     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const;
 
     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;

llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::SETCC,          MVT::v2i16, Custom);
   setOperationAction(ISD::VSELECT,        MVT::v2i16, Custom);
   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8,  Custom);
   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
   setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8,  Custom);
 
   // Subtarget-specific operation actions.
   //
+  if (Subtarget.hasV60TOps()) {
+    setOperationAction(ISD::ROTL, MVT::i32, Custom);
+    setOperationAction(ISD::ROTL, MVT::i64, Custom);
+  }
   if (Subtarget.hasV5TOps()) {
     setOperationAction(ISD::FMA,  MVT::f64, Expand);
     setOperationAction(ISD::FADD, MVT::f64, Expand);
     setOperationAction(ISD::FSUB, MVT::f64, Expand);
     setOperationAction(ISD::FMUL, MVT::f64, Expand);
 
     setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
     setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);

 }
 
 SDValue
 HexagonTargetLowering::LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const {
   return getVectorShiftByInt(Op, DAG);
 }
 
 SDValue
+HexagonTargetLowering::LowerROTL(SDValue Op, SelectionDAG &DAG) const {
+  if (isa<ConstantSDNode>(Op.getOperand(1).getNode()))
+    return Op;
+  return SDValue();
+}
+
+SDValue
 HexagonTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
   MVT ResTy = ty(Op);
   SDValue InpV = Op.getOperand(0);
   MVT InpTy = ty(InpV);
   assert(ResTy.getSizeInBits() == InpTy.getSizeInBits());
   const SDLoc &dl(Op);
 
   // Handle conversion from i8 to v8i1.
#endif
     case ISD::VECTOR_SHUFFLE:       return LowerVECTOR_SHUFFLE(Op, DAG);
     case ISD::BITCAST:              return LowerBITCAST(Op, DAG);
     case ISD::LOAD:                 return LowerUnalignedLoad(Op, DAG);
     case ISD::ADDCARRY:
     case ISD::SUBCARRY:             return LowerAddSubCarry(Op, DAG);
     case ISD::SRA:
     case ISD::SHL:
     case ISD::SRL:                  return LowerVECTOR_SHIFT(Op, DAG);
+    case ISD::ROTL:                 return LowerROTL(Op, DAG);
     case ISD::ConstantPool:         return LowerConstantPool(Op, DAG);
     case ISD::JumpTable:            return LowerJumpTable(Op, DAG);
     case ISD::EH_RETURN:            return LowerEH_RETURN(Op, DAG);
     case ISD::RETURNADDR:           return LowerRETURNADDR(Op, DAG);
     case ISD::FRAMEADDR:            return LowerFRAMEADDR(Op, DAG);
     case ISD::GlobalTLSAddress:     return LowerGlobalTLSAddress(Op, DAG);
     case ISD::ATOMIC_FENCE:         return LowerATOMIC_FENCE(Op, DAG);
     case ISD::GlobalAddress:        return LowerGLOBALADDRESS(Op, DAG);

llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td

 }
 
 
 // Frags for commonly used SDNodes.
 def Add: pf2<add>;    def And: pf2<and>;    def Sra: pf2<sra>;
 def Sub: pf2<sub>;    def Or:  pf2<or>;     def Srl: pf2<srl>;
 def Mul: pf2<mul>;    def Xor: pf2<xor>;    def Shl: pf2<shl>;
 
+def Rol: pf2<rotl>;
 
 // --(1) Immediate -------------------------------------------------------
 //
 
 def SDTHexagonCONST32
   : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<0>]>;
 
 def HexagonJT:          SDNode<"HexagonISD::JT",          SDTIntUnaryOp>;

 
 def: OpR_RR_pat<S2_asr_r_r, Sra, i32, I32, I32>;
 def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>;
 def: OpR_RR_pat<S2_asl_r_r, Shl, i32, I32, I32>;
 def: OpR_RR_pat<S2_asr_r_p, Sra, i64, I64, I32>;
 def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>;
 def: OpR_RR_pat<S2_asl_r_p, Shl, i64, I64, I32>;
 
+let Predicates = [HasV60T] in {
+  def: OpR_RI_pat<S6_rol_i_r, Rol, i32, I32, u5_0ImmPred>;
+  def: OpR_RI_pat<S6_rol_i_p, Rol, i64, I64, u6_0ImmPred>;
+}
 
 def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)),
          (S2_asr_i_r_rnd I32:$Rs, imm:$u5)>;
 def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)),
          (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>, Requires<[HasV5T]>;
 
 // Prefer S2_addasl_rrri over S2_asl_i_r_acc.
 let AddedComplexity = 120 in
let AddedComplexity = 100 in {
   def: AccRRI_pat<S2_asl_i_r_or,    Or,  Su<Shl>, I32, u5_0ImmPred>;
   def: AccRRI_pat<S2_asl_i_r_xacc,  Xor, Su<Shl>, I32, u5_0ImmPred>;
 
   def: AccRRI_pat<S2_asl_i_p_acc,   Add, Su<Shl>, I64, u6_0ImmPred>;
   def: AccRRI_pat<S2_asl_i_p_nac,   Sub, Su<Shl>, I64, u6_0ImmPred>;
   def: AccRRI_pat<S2_asl_i_p_and,   And, Su<Shl>, I64, u6_0ImmPred>;
   def: AccRRI_pat<S2_asl_i_p_or,    Or,  Su<Shl>, I64, u6_0ImmPred>;
   def: AccRRI_pat<S2_asl_i_p_xacc,  Xor, Su<Shl>, I64, u6_0ImmPred>;
+
+  let Predicates = [HasV60T] in {
+    def: AccRRI_pat<S6_rol_i_r_acc,   Add, Su<Rol>, I32, u5_0ImmPred>;
+    def: AccRRI_pat<S6_rol_i_r_nac,   Sub, Su<Rol>, I32, u5_0ImmPred>;
+    def: AccRRI_pat<S6_rol_i_r_and,   And, Su<Rol>, I32, u5_0ImmPred>;
+    def: AccRRI_pat<S6_rol_i_r_or,    Or,  Su<Rol>, I32, u5_0ImmPred>;
+    def: AccRRI_pat<S6_rol_i_r_xacc,  Xor, Su<Rol>, I32, u5_0ImmPred>;
+
+    def: AccRRI_pat<S6_rol_i_p_acc,   Add, Su<Rol>, I64, u6_0ImmPred>;
+    def: AccRRI_pat<S6_rol_i_p_nac,   Sub, Su<Rol>, I64, u6_0ImmPred>;
+    def: AccRRI_pat<S6_rol_i_p_and,   And, Su<Rol>, I64, u6_0ImmPred>;
+    def: AccRRI_pat<S6_rol_i_p_or,    Or,  Su<Rol>, I64, u6_0ImmPred>;
+    def: AccRRI_pat<S6_rol_i_p_xacc,  Xor, Su<Rol>, I64, u6_0ImmPred>;
+  }
 }
 
 let AddedComplexity = 100 in {
   def: AccRRR_pat<S2_asr_r_r_acc,   Add, Su<Sra>, I32, I32, I32>;
   def: AccRRR_pat<S2_asr_r_r_nac,   Sub, Su<Sra>, I32, I32, I32>;
   def: AccRRR_pat<S2_asr_r_r_and,   And, Su<Sra>, I32, I32, I32>;
   def: AccRRR_pat<S2_asr_r_r_or,    Or,  Su<Sra>, I32, I32, I32>;
 

llvm/trunk/test/CodeGen/Hexagon/rotate.ll

+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+target triple = "hexagon"
+
+; CHECK-LABEL: f0
+; CHECK: r0 = rol(r0,#7)
+define i32 @f0(i32 %a0) #0 {
+b0:
+  %v0 = shl i32 %a0, 7
+  %v1 = lshr i32 %a0, 25
+  %v2 = or i32 %v0, %v1
+  ret i32 %v2
+}
+
+; CHECK-LABEL: f1
+; No variable-shift rotates. Check for the default expansion code.
+; This is a rotate left by %a1(r1).
+; CHECK: r[[R10:[0-9]+]] = sub(#32,r1)
+; CHECK: r[[R11:[0-9]+]] = and(r1,#31)
+; CHECK: r[[R12:[0-9]+]] = and(r[[R10]],#31)
+; CHECK: r[[R13:[0-9]+]] = asl(r0,r[[R11]])
+; CHECK: r[[R13]] |= lsr(r0,r[[R12]])
+define i32 @f1(i32 %a0, i32 %a1) #0 {
+b0:
+  %v0 = shl i32 %a0, %a1
+  %v1 = sub i32 32, %a1
+  %v2 = lshr i32 %a0, %v1
+  %v3 = or i32 %v2, %v0
+  ret i32 %v3
+}
+
+; CHECK-LABEL: f2
+; CHECK: r0 = rol(r0,#25)
+define i32 @f2(i32 %a0) #0 {
+b0:
+  %v0 = lshr i32 %a0, 7
+  %v1 = shl i32 %a0, 25
+  %v2 = or i32 %v0, %v1
+  ret i32 %v2
+}
+
+; CHECK-LABEL: f3
+; No variable-shift rotates. Check for the default expansion code.
+; This is a rotate right by %a1(r1) that became a rotate left by 32-%a1.
+; CHECK: r[[R30:[0-9]+]] = sub(#32,r1)
+; CHECK: r[[R31:[0-9]+]] = and(r1,#31)
+; CHECK: r[[R32:[0-9]+]] = and(r[[R30]],#31)
+; CHECK: r[[R33:[0-9]+]] = asl(r0,r[[R32]])
+; CHECK: r[[R33]] |= lsr(r0,r[[R31]])
+define i32 @f3(i32 %a0, i32 %a1) #0 {
+b0:
+  %v0 = lshr i32 %a0, %a1
+  %v1 = sub i32 32, %a1
+  %v2 = shl i32 %a0, %v1
+  %v3 = or i32 %v2, %v0
+  ret i32 %v3
+}
+
+; CHECK-LABEL: f4
+; CHECK: r1:0 = rol(r1:0,#7)
+define i64 @f4(i64 %a0) #0 {
+b0:
+  %v0 = shl i64 %a0, 7
+  %v1 = lshr i64 %a0, 57
+  %v2 = or i64 %v0, %v1
+  ret i64 %v2
+}
+
+; CHECK-LABEL: f5
+; No variable-shift rotates. Check for the default expansion code.
+; This is a rotate left by %a1(r2).
+; CHECK: r[[R50:[0-9]+]] = sub(#64,r2)
+; CHECK: r[[R51:[0-9]+]] = and(r2,#63)
+; CHECK: r[[R52:[0-9]+]] = and(r[[R50]],#63)
+; CHECK: r[[R53:[0-9]+]]:[[R54:[0-9]+]] = asl(r1:0,r[[R51]])
+; CHECK: r[[R53]]:[[R54]] |= lsr(r1:0,r[[R52]])
+define i64 @f5(i64 %a0, i32 %a1) #0 {
+b0:
+  %v0 = zext i32 %a1 to i64
+  %v1 = shl i64 %a0, %v0
+  %v2 = sub i32 64, %a1
+  %v3 = zext i32 %v2 to i64
+  %v4 = lshr i64 %a0, %v3
+  %v5 = or i64 %v4, %v1
+  ret i64 %v5
+}
+
+; CHECK-LABEL: f6
+; CHECK: r1:0 = rol(r1:0,#57)
+define i64 @f6(i64 %a0) #0 {
+b0:
+  %v0 = lshr i64 %a0, 7
+  %v1 = shl i64 %a0, 57
+  %v2 = or i64 %v0, %v1
+  ret i64 %v2
+}
+
+; CHECK-LABEL: f7
+; No variable-shift rotates. Check for the default expansion code.
+; This is a rotate right by %a1(r2) that became a rotate left by 64-%a1.
+; CHECK: r[[R70:[0-9]+]] = sub(#64,r2)
+; CHECK: r[[R71:[0-9]+]] = and(r2,#63)
+; CHECK: r[[R72:[0-9]+]] = and(r[[R70]],#63)
+; CHECK: r[[R73:[0-9]+]]:[[R75:[0-9]+]] = asl(r1:0,r[[R72]])
+; CHECK: r[[R73]]:[[R75]] |= lsr(r1:0,r[[R71]])
+define i64 @f7(i64 %a0, i32 %a1) #0 {
+b0:
+  %v0 = zext i32 %a1 to i64
+  %v1 = lshr i64 %a0, %v0
+  %v2 = sub i32 64, %a1
+  %v3 = zext i32 %v2 to i64
+  %v4 = shl i64 %a0, %v3
+  %v5 = or i64 %v4, %v1
+  ret i64 %v5
+}
+
+; CHECK-LABEL: f8
+; CHECK: r0 += rol(r1,#7)
+define i32 @f8(i32 %a0, i32 %a1) #0 {
+b0:
+  %v0 = shl i32 %a1, 7
+  %v1 = lshr i32 %a1, 25
+  %v2 = or i32 %v0, %v1
+  %v3 = add i32 %v2, %a0
+  ret i32 %v3
+}
+
+; CHECK-LABEL: f9
+; CHECK: r0 -= rol(r1,#7)
+define i32 @f9(i32 %a0, i32 %a1) #0 {
+b0:
+  %v0 = shl i32 %a1, 7
+  %v1 = lshr i32 %a1, 25
+  %v2 = or i32 %v0, %v1
+  %v3 = sub i32 %a0, %v2
+  ret i32 %v3
+}
+
+; CHECK-LABEL: f10
+; CHECK: r0 &= rol(r1,#7)
+define i32 @f10(i32 %a0, i32 %a1) #0 {
+b0:
+  %v0 = shl i32 %a1, 7
+  %v1 = lshr i32 %a1, 25
+  %v2 = or i32 %v0, %v1
+  %v3 = and i32 %v2, %a0
+  ret i32 %v3
+}
+
+; CHECK-LABEL: f12
+; CHECK: r0 ^= rol(r1,#7)
+define i32 @f12(i32 %a0, i32 %a1) #0 {
+b0:
+  %v0 = shl i32 %a1, 7
+  %v1 = lshr i32 %a1, 25
+  %v2 = or i32 %v0, %v1
+  %v3 = xor i32 %v2, %a0
+  ret i32 %v3
+}
+
+; CHECK-LABEL: f13
+; CHECK: r1:0 += rol(r3:2,#7)
+define i64 @f13(i64 %a0, i64 %a1) #0 {
+b0:
+  %v0 = shl i64 %a1, 7
+  %v1 = lshr i64 %a1, 57
+  %v2 = or i64 %v0, %v1
+  %v3 = add i64 %v2, %a0
+  ret i64 %v3
+}
+
+; CHECK-LABEL: f14
+; CHECK: r1:0 -= rol(r3:2,#7)
+define i64 @f14(i64 %a0, i64 %a1) #0 {
+b0:
+  %v0 = shl i64 %a1, 7
+  %v1 = lshr i64 %a1, 57
+  %v2 = or i64 %v0, %v1
+  %v3 = sub i64 %a0, %v2
+  ret i64 %v3
+}
+
+; CHECK-LABEL: f15
+; CHECK: r1:0 &= rol(r3:2,#7)
+define i64 @f15(i64 %a0, i64 %a1) #0 {
+b0:
+  %v0 = shl i64 %a1, 7
+  %v1 = lshr i64 %a1, 57
+  %v2 = or i64 %v0, %v1
+  %v3 = and i64 %v2, %a0
+  ret i64 %v3
+}
+
+; CHECK-LABEL: f17
+; CHECK: r1:0 ^= rol(r3:2,#7)
+define i64 @f17(i64 %a0, i64 %a1) #0 {
+b0:
+  %v0 = shl i64 %a1, 7
+  %v1 = lshr i64 %a1, 57
+  %v2 = or i64 %v0, %v1
+  %v3 = xor i64 %v2, %a0
+  ret i64 %v3
+}
+
+attributes #0 = { norecurse nounwind readnone "target-cpu"="hexagonv60" "target-features"="-packets" }

llvm/trunk/test/CodeGen/Hexagon/rotl-i64.ll

 ; RUN: llc -march=hexagon < %s | FileCheck %s
-; CHECK: asl
+; CHECK: rol
 
 ; Function Attrs: nounwind
 define fastcc void @f0() #0 {
 b0:
   br label %b1
 
 b1:                                               ; preds = %b1, %b0
   br i1 undef, label %b2, label %b1
 
 b2:                                               ; preds = %b1
   br label %b3
 
 b3:                                               ; preds = %b3, %b2
   %v0 = load i64, i64* undef, align 8, !tbaa !0
   %v1 = lshr i64 %v0, 8
   %v2 = shl i64 %v0, 56
   %v3 = or i64 %v2, %v1
   %v4 = xor i64 %v3, 0
   %v5 = xor i64 %v4, 0
   %v6 = add i64 0, %v5
   store i64 %v6, i64* undef, align 8, !tbaa !0
   br label %b3
 }
 
-attributes #0 = { nounwind }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" }
 
 !0 = !{!1, !1, i64 0}
 !1 = !{!"long long", !2}
 !2 = !{!"omnipotent char", !3}
 !3 = !{!"Simple C/C++ TBAA"}