AMDGPU: Preserve metadata when widening loads

[arsenm]

I'm not entirely sure it's correct to preserve the high part of the range, since nothing is guaranteed about the high bits

[arsenm]

Apparently !range allows multiple disjoint segments, so this needs more work

[arsenm]

Don't use high range

[rampitec]

lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp

489

Range is [a, b). I.e. upper bound is not included in the range. But range can wrap around so 0 should work.
At the same time you will need to check that lower bound is not zero then because it is required that a != b.

[arsenm]

Fix upper bound and drop if 0

[rampitec]

LGTM

[arsenm]

r334045

lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp

bool AMDGPUCodeGenPrepare::visitBinaryOperator(BinaryOperator &I) {
 
   if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) &&
       DA->isUniform(&I))
     Changed |= promoteUniformOpToI32(I);
 
   return Changed;
 }
 
-bool AMDGPUCodeGenPrepare::visitLoadInst(LoadInst  &I) {
+bool AMDGPUCodeGenPrepare::visitLoadInst(LoadInst &I) {
   if ((I.getPointerAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS ||
        I.getPointerAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS_32BIT) &&
       canWidenScalarExtLoad(I)) {
     IRBuilder<> Builder(&I);
     Builder.SetCurrentDebugLocation(I.getDebugLoc());
 
     Type *I32Ty = Builder.getInt32Ty();
     Type *PT = PointerType::get(I32Ty, I.getPointerAddressSpace());
     Value *BitCast= Builder.CreateBitCast(I.getPointerOperand(), PT);
-    Value *WidenLoad = Builder.CreateLoad(BitCast);
+    LoadInst *WidenLoad = Builder.CreateLoad(BitCast);
+    WidenLoad->copyMetadata(I);
+
+    // If we have range metadata, we need to convert the type, and not make
+    // assumptions about the high bits.
+    if (auto *Range = WidenLoad->getMetadata(LLVMContext::MD_range)) {
+      ConstantInt *Lower =
+        mdconst::extract<ConstantInt>(Range->getOperand(0));
+
+      if (Lower->getValue().isNullValue()) {
+        WidenLoad->setMetadata(LLVMContext::MD_range, nullptr);
+      } else {
+        Metadata *LowAndHigh[] = {
+          ConstantAsMetadata::get(ConstantInt::get(I32Ty, Lower->getValue().zext(32))),
+          // Don't make assumptions about the high bits.
+          ConstantAsMetadata::get(ConstantInt::get(I32Ty, 0))
+        };
+
+        WidenLoad->setMetadata(LLVMContext::MD_range,
+                               MDNode::get(Mod->getContext(), LowAndHigh));
+      }
+    }
 
     int TySize = Mod->getDataLayout().getTypeSizeInBits(I.getType());
     Type *IntNTy = Builder.getIntNTy(TySize);
     Value *ValTrunc = Builder.CreateTrunc(WidenLoad, IntNTy);
     Value *ValOrig = Builder.CreateBitCast(ValTrunc, I.getType());
     I.replaceAllUsesWith(ValOrig);
     I.eraseFromParent();
     return true;

test/CodeGen/AMDGPU/widen_extending_scalar_loads.ll

 define amdgpu_kernel void @use_dispatch_ptr(i32 addrspace(1)* %ptr) #1 {
   %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
   %val = load i8, i8 addrspace(4)* %dispatch.ptr, align 4
   %ld = zext i8 %val to i32
   store i32 %ld, i32 addrspace(1)* %ptr
   ret void
 }
 
+; OPT-LABEL: @constant_load_i16_align4_range(
+; OPT: load i32, i32 addrspace(4)* %1, !range !0
+define amdgpu_kernel void @constant_load_i16_align4_range(i32 addrspace(1)* %out, i16 addrspace(4)* %in) #0 {
+  %ld = load i16, i16 addrspace(4)* %in, align 4, !range !0
+  %ext = sext i16 %ld to i32
+  store i32 %ext, i32 addrspace(1)* %out
+  ret void
+}
+
+; OPT-LABEL: @constant_load_i16_align4_range_max(
+; OPT: load i32, i32 addrspace(4)* %1, !range !0
+define amdgpu_kernel void @constant_load_i16_align4_range_max(i32 addrspace(1)* %out, i16 addrspace(4)* %in) #0 {
+  %ld = load i16, i16 addrspace(4)* %in, align 4, !range !1
+  %ext = sext i16 %ld to i32
+  store i32 %ext, i32 addrspace(1)* %out
+  ret void
+}
+
+; OPT-LABEL: @constant_load_i16_align4_complex_range(
+; OPT: load i32, i32 addrspace(4)* %1, !range !1
+define amdgpu_kernel void @constant_load_i16_align4_complex_range(i32 addrspace(1)* %out, i16 addrspace(4)* %in) #0 {
+  %ld = load i16, i16 addrspace(4)* %in, align 4, !range !2
+  %ext = sext i16 %ld to i32
+  store i32 %ext, i32 addrspace(1)* %out
+  ret void
+}
+
+; OPT-LABEL: @constant_load_i16_align4_range_from_0(
+; OPT: load i32, i32 addrspace(4)* %1{{$}}
+define amdgpu_kernel void @constant_load_i16_align4_range_from_0(i32 addrspace(1)* %out, i16 addrspace(4)* %in) #0 {
+  %ld = load i16, i16 addrspace(4)* %in, align 4, !range !3
+  %ext = sext i16 %ld to i32
+  store i32 %ext, i32 addrspace(1)* %out
+  ret void
+}
+
+; OPT-LABEL: @constant_load_i16_align4_range_from_neg(
+; OPT: load i32, i32 addrspace(4)* %1, !range !2
+define amdgpu_kernel void @constant_load_i16_align4_range_from_neg(i32 addrspace(1)* %out, i16 addrspace(4)* %in) #0 {
+  %ld = load i16, i16 addrspace(4)* %in, align 4, !range !4
+  %ext = sext i16 %ld to i32
+  store i32 %ext, i32 addrspace(1)* %out
+  ret void
+}
+
+; OPT-LABEL: @constant_load_i16_align4_range_from_neg_to_0(
+; OPT: load i32, i32 addrspace(4)* %1, !range !2
+define amdgpu_kernel void @constant_load_i16_align4_range_from_neg_to_0(i32 addrspace(1)* %out, i16 addrspace(4)* %in) #0 {
+  %ld = load i16, i16 addrspace(4)* %in, align 4, !range !5
+  %ext = sext i16 %ld to i32
+  store i32 %ext, i32 addrspace(1)* %out
+  ret void
+}
+
+; OPT-LABEL: @constant_load_i16_align4_invariant
+; OPT: load i32, i32 addrspace(4)* %1, !invariant.load !3
+define amdgpu_kernel void @constant_load_i16_align4_invariant(i32 addrspace(1)* %out, i16 addrspace(4)* %in) #0 {
+  %ld = load i16, i16 addrspace(4)* %in, align 4, !invariant.load !6
+  %ext = sext i16 %ld to i32
+  store i32 %ext, i32 addrspace(1)* %out
+  ret void
+}
+
+
 attributes #0 = { nounwind }
+
+; OPT: !0 = !{i32 5, i32 0}
+; OPT: !1 = !{i32 8, i32 0}
+; OPT: !2 = !{i32 65520, i32 0}
+; OPT: !3 = !{}
+
+
+!0 = !{i16 5, i16 500}
+!1 = !{i16 5, i16 -1}
+!2 = !{i16 8, i16 12, i16 42, i16 99}
+!3 = !{i16 0, i16 255}
+!4 = !{i16 -16, i16 16}
+!5 = !{i16 -16, i16 0}
+!6 = !{}