[mips] Guard all short instructions correctly.

[atanasyan]

LGTM

lib/Target/Mips/MicroMips32r6InstrInfo.td

def : MipsInstAlias<"xor $rs, $imm",
                     (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
                     ISA_MICROMIPS32R6;
 def : MipsInstAlias<"not $rt, $rs",
                     (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
                     ISA_MICROMIPS32R6;
 def : MipsInstAlias<"lapc $rd, $imm",
                     (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
                     ISA_MICROMIPS32R6;
-
+def : MipsInstAlias<"beqz16 $rs, $offset", (BEQZC16_MMR6 GPRMM16Opnd:$rs,
+                                                         brtarget7_mm:$offset),
+                    0>, ISA_MICROMIPS32R6;
+def : MipsInstAlias<"bnez16 $rs, $offset", (BNEZC16_MMR6 GPRMM16Opnd:$rs,
+                                                         brtarget7_mm:$offset),
+                    0>, ISA_MICROMIPS32R6;
+def : MipsInstAlias<"b16 $offset", (BC16_MMR6 brtarget10_mm:$offset), 0>,
+                    ISA_MICROMIPS32R6;
 //===----------------------------------------------------------------------===//
 //
 // MicroMips arbitrary patterns that map to one or more instructions
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
               (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;

lib/Target/Mips/MicroMipsInstrInfo.td

 
 let FastISelShouldIgnore = 1 in {
   def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
                   ARITH_FM_MM16<1>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
                  LOGIC_FM_MM16<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6;
 }
 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
-                        mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
+                        mem_mm_4>, LOAD_STORE_FM_MM16<0x02>, ISA_MICROMIPS;
 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
-                        mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
+                        mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>, ISA_MICROMIPS;
 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
-                      LOAD_STORE_FM_MM16<0x1a>;
+                      LOAD_STORE_FM_MM16<0x1a>, ISA_MICROMIPS;
 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
-                        II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
+                        II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>,
+                        ISA_MICROMIPS32_NOT_MIPS32R6;
 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
                         II_SH, mem_mm_4_lsl1>,
-                        LOAD_STORE_FM_MM16<0x2a>;
+                        LOAD_STORE_FM_MM16<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6;
 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
-                        mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
+                        mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>,
+                        ISA_MICROMIPS32_NOT_MIPS32R6;
 def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_simm7_lsl2>,
-                         LOAD_GP_FM_MM16<0x19>;
+                         LOAD_GP_FM_MM16<0x19>, ISA_MICROMIPS;
 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
-              LOAD_STORE_SP_FM_MM16<0x12>;
+              LOAD_STORE_SP_FM_MM16<0x12>, ISA_MICROMIPS;
 def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
-              LOAD_STORE_SP_FM_MM16<0x32>;
-def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
-def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
-def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
-def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
+              LOAD_STORE_SP_FM_MM16<0x32>, ISA_MICROMIPS32_NOT_MIPS32R6;
+def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16,
+                   ISA_MICROMIPS;
+def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16,
+                 ISA_MICROMIPS;
+def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16,
+                 ISA_MICROMIPS;
+def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16, ISA_MICROMIPS;
 def MFHI16_MM : MoveFromHILOMM<"mfhi16", GPR32Opnd, AC0>,
                 MFHILO_FM_MM16<0x10>, ISA_MICROMIPS32_NOT_MIPS32R6;
 def MFLO16_MM : MoveFromHILOMM<"mflo16", GPR32Opnd, AC0>,
                 MFHILO_FM_MM16<0x12>, ISA_MICROMIPS32_NOT_MIPS32R6;
-def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
+def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>,
+                ISA_MICROMIPS32_NOT_MIPS32R6;
 def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16,
                ISA_MICROMIPS32_NOT_MIPS32R6;
 def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16,
-              IsAsCheapAsAMove;
+              IsAsCheapAsAMove, ISA_MICROMIPS32_NOT_MIPS32R6;
 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
                 ISA_MICROMIPS32_NOT_MIPS32R6;
-def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
-def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
-def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
-def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
+def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>,
+                 ISA_MICROMIPS32_NOT_MIPS32R6;
+def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>,
+               ISA_MICROMIPS32_NOT_MIPS32R6;
+def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>,
+                ISA_MICROMIPS32_NOT_MIPS32R6;
+def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>,
+              ISA_MICROMIPS32_NOT_MIPS32R6;
 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
-                BEQNEZ_FM_MM16<0x23>;
+                BEQNEZ_FM_MM16<0x23>, ISA_MICROMIPS32_NOT_MIPS32R6;
 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
-                BEQNEZ_FM_MM16<0x2b>;
-def B16_MM : UncondBranchMM16<"b16">, B16_FM;
+                BEQNEZ_FM_MM16<0x2b>, ISA_MICROMIPS32_NOT_MIPS32R6;
+def B16_MM : UncondBranchMM16<"b16">, B16_FM, ISA_MICROMIPS32_NOT_MIPS32R6;
 def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>,
                  ISA_MICROMIPS32_NOT_MIPS32R6;
 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>,
                  ISA_MICROMIPS32_NOT_MIPS32R6;
 
 let DecoderNamespace = "MicroMips" in {
   /// Load and Store Instructions - multiple
   def SWM16_MM : StoreMultMM16<"swm16", II_SWM>, LWM_FM_MM16<0x5>,

test/MC/Mips/micromips-neg-offset.s

 # Check decoding beqz instruction with a negative offset
 
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
 # RUN:         -mattr=micromips -mcpu=mips32r6 %s -o - \
 # RUN:   | llvm-objdump -d -mattr=micromips - | FileCheck %s
 
 # CHECK: 0:   8f 7e        beqzc16  $6, -4
-# CHECK: 6:   cf fe        bc16     -4
-# CHECK: c:   b7 ff ff fe  balc     -4
+# CHECK: 2:   cf fe        bc16     -4
+# CHECK: 4:   b7 ff ff fe  balc     -4
 
 beqz16  $6, -4
 b16     -4
 balc    -4

test/MC/Mips/micromips/valid.s

 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mattr=micromips,eva | FileCheck %s
 
 .set noat
 addiusp -16                 # CHECK: addiusp -16        # encoding: [0x4f,0xf9]
+                            # CHECK:                    # <MCInst #{{.*}} ADDIUSP_MM
 addiusp -1028               # CHECK: addiusp -1028      # encoding: [0x4f,0xff]
+                            # CHECK:                    # <MCInst #{{.*}} ADDIUSP_MM
 addiusp -1032               # CHECK: addiusp -1032      # encoding: [0x4f,0xfd]
+                            # CHECK:                    # <MCInst #{{.*}} ADDIUSP_MM
 addiusp 1024                # CHECK: addiusp 1024       # encoding: [0x4c,0x01]
+                            # CHECK:                    # <MCInst #{{.*}} ADDIUSP_MM
 addiusp 1028                # CHECK: addiusp 1028       # encoding: [0x4c,0x03]
+                            # CHECK:                    # <MCInst #{{.*}} ADDIUSP_MM
 andi16 $16, $2, 31          # CHECK: andi16 $16, $2, 31 # encoding: [0x2c,0x29]
+                            # CHECK:                    # <MCInst #{{.*}} ANDI16_MM
 jraddiusp 20                # CHECK: jraddiusp 20       # encoding: [0x47,0x05]
+                            # CHECK:                    # <MCInst #{{.*}} JRADDIUSP
 addu16 $6, $17, $4          # CHECK: addu16 $6, $17, $4 # encoding: [0x07,0x42]
+                            # CHECK:                    # <MCInst #{{.*}} ADDU16_MM
 subu16 $5, $16, $3          # CHECK: subu16 $5, $16, $3 # encoding: [0x06,0xb1]
+                            # CHECK:                    # <MCInst #{{.*}} SUBU16_MM
 and16 $16, $2               # CHECK: and16 $16, $2      # encoding: [0x44,0x82]
+                            # CHECK:                    # <MCInst #{{.*}} AND16_MM
 not16 $17, $3               # CHECK: not16 $17, $3      # encoding: [0x44,0x0b]
+                            # CHECK:                    # <MCInst #{{.*}} NOT16_MM
 or16 $16, $4                # CHECK: or16 $16, $4       # encoding: [0x44,0xc4]
+                            # CHECK:                    # <MCInst #{{.*}} OR16_MM
 xor16 $17, $5               # CHECK: xor16 $17, $5      # encoding: [0x44,0x4d]
+                            # CHECK:                    # <MCInst #{{.*}} XOR16_MM
 sll16 $3, $16, 5            # CHECK: sll16 $3, $16, 5   # encoding: [0x25,0x8a]
+                            # CHECK:                    # <MCInst #{{.*}} SLL16_MM
 srl16 $4, $17, 6            # CHECK: srl16 $4, $17, 6   # encoding: [0x26,0x1d]
+                            # CHECK:                    # <MCInst #{{.*}} SRL16_MM
 lbu16 $3, 4($17)            # CHECK: lbu16 $3, 4($17)   # encoding: [0x09,0x94]
+                            # CHECK:                    # <MCInst #{{.*}} LBU16_MM
 lbu16 $3, -1($16)           # CHECK: lbu16 $3, -1($16)  # encoding: [0x09,0x8f]
+                            # CHECK:                    # <MCInst #{{.*}} LBU16_MM
 lhu16 $3, 4($16)            # CHECK: lhu16 $3, 4($16)   # encoding: [0x29,0x82]
+                            # CHECK:                    # <MCInst #{{.*}} LHU16_MM
 lw16 $4, 8($17)             # CHECK: lw16 $4, 8($17)    # encoding: [0x6a,0x12]
+                            # CHECK:                    # <MCInst #{{.*}} LW16_MM
 sb16 $3, 4($16)             # CHECK: sb16 $3, 4($16)    # encoding: [0x89,0x84]
+                            # CHECK:                    # <MCInst #{{.*}} SB16_MM
 sh16 $4, 8($17)             # CHECK: sh16 $4, 8($17)    # encoding: [0xaa,0x14]
+                            # CHECK:                    # <MCInst #{{.*}} SH16_MM
 sw16 $4, 4($17)             # CHECK: sw16 $4, 4($17)    # encoding: [0xea,0x11]
+                            # CHECK:                    # <MCInst #{{.*}} SW16_MM
 sw16 $zero, 4($17)          # CHECK: sw16 $zero, 4($17) # encoding: [0xe8,0x11]
+                            # CHECK:                    # <MCInst #{{.*}} SW16_MM
 mfhi16 $9                   # CHECK: mfhi16 $9          # encoding: [0x46,0x09]
+                            # CHECK:                    # <MCInst #{{.*}} MFHI16_MM
 mflo16 $9                   # CHECK: mflo16 $9          # encoding: [0x46,0x49]
+                            # CHECK:                    # <MCInst #{{.*}} MFLO16_MM
 move $25, $1                # CHECK: move $25, $1       # encoding: [0x0f,0x21]
+                            # CHECK:                    # <MCInst #{{.*}} MOVE16_MM
 jrc $9                      # CHECK: jrc $9             # encoding: [0x45,0xa9]
+                            # CHECK:                    # <MCInst #{{.*}} JRC16_MM
 jalr $9                     # CHECK: jalr $9            # encoding: [0x45,0xc9]
+                            # CHECK:                    # <MCInst #{{.*}} JALR16_MM
 jalrs16 $9                  # CHECK: jalrs16 $9         # encoding: [0x45,0xe9]
+                            # CHECK:                    # <MCInst #{{.*}} MOVE16_MM
 jr16 $9                     # CHECK: jr16 $9            # encoding: [0x45,0x89]
+                            # CHECK:                    # <MCInst #{{.*}} JR16_MM
 li16 $3, -1                 # CHECK: li16 $3, -1        # encoding: [0xed,0xff]
+                            # CHECK:                    # <MCInst #{{.*}} LI16_MM
 li16 $3, 126                # CHECK: li16 $3, 126       # encoding: [0xed,0xfe]
+                            # CHECK:                    # <MCInst #{{.*}} LI16_MM
 addiur1sp $7, 4             # CHECK: addiur1sp $7, 4    # encoding: [0x6f,0x83]
+                            # CHECK:                    # <MCInst #{{.*}} ADDIUR1SP_MM
 addiur2 $6, $7, -1          # CHECK: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
+                            # CHECK:                    # <MCInst #{{.*}} ADDIUR2_MM
 addiur2 $6, $7, 12          # CHECK: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
+                            # CHECK:                    # <MCInst #{{.*}} ADDIUR2_MM
 addius5 $7, -2              # CHECK: addius5 $7, -2     # encoding: [0x4c,0xfc]
 nop                         # CHECK: nop                # encoding: [0x00,0x00,0x00,0x00]
 beqz16 $6, 20               # CHECK: beqz16 $6, 20      # encoding: [0x8f,0x0a]
+                            # CHECK:                    # <MCInst #{{.*}} BEQZ16_MM
 bnez16 $6, 20               # CHECK: bnez16 $6, 20      # encoding: [0xaf,0x0a]
+                            # CHECK:                    # <MCInst #{{.*}} BNEZ16_MM
 b16 132                     # CHECK: b16 132            # encoding: [0xcc,0x42]
+                            # CHECK:                    # <MCInst #{{.*}} B16_MM
 lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12]
+                            # CHECK:                             # <MCInst #{{.*}} LWM16_MM
 swm16 $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52]
-movep $5, $6, $2, $3        # CHECK: movep $5, $6, $2, $3        # encoding: [0x84,0x34]
-break16 8                   # CHECK: break16 8          # encoding: [0x46,0x88]
-sdbbp16 14                  # CHECK: sdbbp16 14         # encoding: [0x46,0xce]
-lw $3, 32($sp)              # CHECK: lw $3, 32($sp)     # encoding: [0x48,0x68]
-sw $4, 124($sp)             # CHECK: sw $4, 124($sp)    # encoding: [0xc8,0x9f]
-lw $3, 32($gp)              # CHECK: lw $3, 32($gp)     # encoding: [0x65,0x88]
+                            # CHECK:                      # <MCInst #{{.*}} SWM16_MM
+movep $5, $6, $2, $3        # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
+                            # CHECK:                      # <MCInst #{{.*}} MOVEP_MM
+break16 8                   # CHECK: break16 8            # encoding: [0x46,0x88]
+                            # CHECK:                      # <MCInst #{{.*}} BREAK16_MM
+sdbbp16 14                  # CHECK: sdbbp16 14           # encoding: [0x46,0xce]
+                            # CHECK:                      # <MCInst #{{.*}} SDBBP16_MM
+lw $3, 32($sp)              # CHECK: lw $3, 32($sp)       # encoding: [0x48,0x68]
+                            # CHECK:                      # <MCInst #{{.*}} LWSP_MM
+sw $4, 124($sp)             # CHECK: sw $4, 124($sp)      # encoding: [0xc8,0x9f]
+                            # CHECK:                      # <MCInst #{{.*}} SWSP_MM
+lw $3, 32($gp)              # CHECK: lw $3, 32($gp)       # encoding: [0x65,0x88]
+                            # CHECK:                      # <MCInst #{{.*}} LWGP_MM
 abs.s $f0, $f2              # CHECK:  abs.s $f0, $f2    # encoding: [0x54,0x02,0x03,0x7b]
                             # CHECK-NEXT:               # <MCInst #{{[0-9]+}} FABS_S_MM
 abs.d $f4, $f6              # CHECK:  abs.d $f4, $f6    # encoding: [0x54,0x86,0x23,0x7b]
                             # CHECK-NEXT:               # <MCInst #{{[0-9]+}} FABS_D32_MM
 sqrt.s  $f0, $f12           # CHECK:  sqrt.s  $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b]
                             # CHECK-NEXT:               # <MCInst #{{[0-9]+}} FSQRT_S_MM
 sqrt.d  $f0, $f12           # CHECK:  sqrt.d  $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b]
                             # CHECK-NEXT:               # <MCInst #{{[0-9]+}} FSQRT_D32_MM

test/MC/Mips/micromips32r6/valid.s

 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r6 -mattr=micromips | FileCheck %s
 
   .set noat
   add $3, $4, $5           # CHECK: add $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x10]
   addiu $3, $4, 1234       # CHECK: addiu $3, $4, 1234  # encoding: [0x30,0x64,0x04,0xd2]
   addu $3, $4, $5          # CHECK: addu $3, $4, $5     # encoding: [0x00,0xa4,0x19,0x50]
   addiupc $4, 100          # CHECK: lapc $4, 100        # encoding: [0x78,0x80,0x00,0x19]
   addiur1sp $7, 4          # CHECK: addiur1sp $7, 4     # encoding: [0x6f,0x83]
+                           # CHECK:                     # <MCInst #{{.*}} ADDIUR1SP_MM
   addiur2 $6, $7, -1       # CHECK: addiur2 $6, $7, -1  # encoding: [0x6f,0x7e]
+                           # CHECK:                     # <MCInst #{{.*}} ADDIUR2_MM
   addiur2 $6, $7, 12       # CHECK: addiur2 $6, $7, 12  # encoding: [0x6f,0x76]
+                           # CHECK:                     # <MCInst #{{.*}} ADDIUR2_MM
   addius5 $7, -2           # CHECK: addius5 $7, -2      # encoding: [0x4c,0xfc]
+                           # CHECK:                     # <MCInst #{{.*}} ADDIUS5_MM
   addiusp -1028            # CHECK: addiusp -1028       # encoding: [0x4f,0xff]
+                           # CHECK:                     # <MCInst #{{.*}} ADDIUSP_MM
   addiusp -1032            # CHECK: addiusp -1032       # encoding: [0x4f,0xfd]
+                           # CHECK:                     # <MCInst #{{.*}} ADDIUSP_MM
   addiusp 1024             # CHECK: addiusp 1024        # encoding: [0x4c,0x01]
+                           # CHECK:                     # <MCInst #{{.*}} ADDIUSP_MM
   addiusp 1028             # CHECK: addiusp 1028        # encoding: [0x4c,0x03]
+                           # CHECK:                     # <MCInst #{{.*}} ADDIUSP_MM
   addiusp -16              # CHECK: addiusp -16         # encoding: [0x4f,0xf9]
+                           # CHECK:                     # <MCInst #{{.*}} ADDIUSP_MM
   aluipc $3, 56            # CHECK: aluipc $3, 56       # encoding: [0x78,0x7f,0x00,0x38]
   and $3, $4, $5           # CHECK: and $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0x50]
   andi $3, $4, 1234        # CHECK: andi $3, $4, 1234   # encoding: [0xd0,0x64,0x04,0xd2]
   auipc $3, -1             # CHECK: auipc $3, -1        # encoding: [0x78,0x7e,0xff,0xff]
   align $4, $2, $3, 2      # CHECK: align $4, $2, $3, 2 # encoding: [0x00,0x43,0x24,0x1f]
   aui $3,$2,23             # CHECK: aui $3, $2, 23      # encoding: [0x10,0x62,0x00,0x17]
   beqc $3,$4, 16           # CHECK: beqc    $3, $4, 16  # encoding: [0x74,0x83,0x00,0x04]
   bgec $3,$4, 16           # CHECK: bgec    $3, $4, 16  # encoding: [0xf4,0x83,0x00,0x04]
   bgeuc $3,$4, 16          # CHECK: bgeuc   $3, $4, 16  # encoding: [0xc0,0x83,0x00,0x04]
   bltc $3,$4, 16           # CHECK: bltc    $3, $4, 16  # encoding: [0xd4,0x83,0x00,0x04]
   bltuc $3,$4, 16          # CHECK: bltuc   $3, $4, 16  # encoding: [0xe0,0x83,0x00,0x04]
   bnec $3,$4, 16           # CHECK: bnec    $3, $4, 16  # encoding: [0x7c,0x83,0x00,0x04]
   beqzalc $2, 1332         # CHECK: beqzalc $2, 1332    # encoding: [0x74,0x40,0x02,0x9a]
   bnezalc $2, 1332         # CHECK: bnezalc $2, 1332    # encoding: [0x7c,0x40,0x02,0x9a]
   bgezalc $2, 1332         # CHECK: bgezalc $2, 1332    # encoding: [0xc0,0x42,0x02,0x9a]
   bgtzalc $2, 1332         # CHECK: bgtzalc $2, 1332    # encoding: [0xe0,0x40,0x02,0x9a]
   bltzalc $2, 1332         # CHECK: bltzalc $2, 1332    # encoding: [0xe0,0x42,0x02,0x9a]
   blezalc $2, 1332         # CHECK: blezalc $2, 1332    # encoding: [0xc0,0x40,0x02,0x9a]
   beqzc   $3, 64           # CHECK: beqzc   $3, 64      # encoding: [0x80,0x60,0x00,0x10]
   bnezc   $3, 64           # CHECK: bnezc   $3, 64      # encoding: [0xa0,0x60,0x00,0x10]
   balc 7286128             # CHECK: balc 7286128        # encoding: [0xb4,0x37,0x96,0xb8]
   b 132                    # CHECK: bc16 132            # encoding: [0xcc,0x42]
+                           # CHECK:                     # <MCInst #{{.*}} BC16_MMR6
   bc 7286128               # CHECK: bc 7286128          # encoding: [0x94,0x37,0x96,0xb8]
-                           # CHECK-NEXT:                # <MCInst #{{[0-9]+}} BC_MMR6
+                           # CHECK:                     # <MCInst #{{.*}} BC_MMR6
   bc16 132                 # CHECK: bc16 132            # encoding: [0xcc,0x42]
-  beqzc16 $6, 20           # CHECK: beqzc16 $6, 20      # encoding: [0x8f,0x0a]
-  bnezc16 $6, 20           # CHECK: bnezc16 $6, 20      # encoding: [0xaf,0x0a]
+                           # CHECK:                     # <MCInst #{{.*}} BC16_MMR6
+  beqzc16 $6, 20           # CHECK: beqzc16  $6, 20     # encoding: [0x8f,0x0a]
+                           # CHECK:                     # <MCInst #{{.*}} BEQZC16_MMR6
+  bnezc16 $6, 20           # CHECK: bnezc16  $6, 20     # encoding: [0xaf,0x0a]
+                           # CHECK:                     # <MCInst #{{.*}} BNEZC16_MMR6
   bitswap $4, $2           # CHECK: bitswap $4, $2      # encoding: [0x00,0x44,0x0b,0x3c]
   break                    # CHECK: break               # encoding: [0x00,0x00,0x00,0x07]
   break 7                  # CHECK: break 7             # encoding: [0x00,0x07,0x00,0x07]
   break 7, 5               # CHECK: break 7, 5          # encoding: [0x00,0x07,0x01,0x47]
   cache 1, 8($5)           # CHECK: cache 1, 8($5)      # encoding: [0x20,0x25,0x60,0x08]
                            # CHECK-NEXT:                # <MCInst #{{.*}} CACHE_MMR6
   clo $11, $a1             # CHECK: clo $11, $5         # encoding: [0x01,0x65,0x4b,0x3c]
   clz $sp, $gp             # CHECK: clz $sp, $gp        # encoding: [0x03,0x80,0xe8,0x50]