[X86][Sched] Fix WriteZero sched class for all CPUs.

[courbet]

Summary

Because the default latency and #uops are 1 in a WriteRes, they were
wrong for WriteZero.

[RKSimon]

TBH, WriteZero really isn't fit for purpose - its trying to do too much, and with a bit of luck we might be able to get rid of most of it:

FLD1/FLDZ (write f80 constants) seem to always use a resource of some kind - I haven't investigated too much into how they should be tagged although a quick glance at Agner suggests they reasonably match CVTPI2PD (so maybe retag them as WriteCvtI2PD?), or maybe create a WriteF80Constant class - same for the other x87 constants - FLDPI/FLDLG2/FLDL2E/FLDL2T/FLDLN2 as they typically are all the same (although incorrectly set to WriteMicrocoded by the looks of the tests).

The xmm/ymm/gpr zero idioms will hopefully be handled by variants (see D47374 which gets more of this in place) - not sure what to do with the zero psuedo instructions, maybe keep WriteZero just for them (or move into WriteNOP)?

The remaining cases (CLC etc.) might almost be better off using WriteNOP, or a target specific equivalent.

[courbet]

rebase

[RKSimon]

lib/Target/X86/X86SchedBroadwell.td

159

You can make all of these tidier by using the X86WriteRes multiclass:

defm : X86WriteRes<WriteZero, [], 0, [], 0>;

test/CodeGen/X86/avx512-intrinsics-upgrade.ll

2

General intrinsics/combines tests shouldn't typically be dependent on a specific cpu model - it causes superfluous changes like these - I'll fix the tests shortly.

utils/TableGen/GlobalISelEmitter.cpp

1987

Should this be here?

[RKSimon]

@courbet What's the plan for this phab?

[courbet]

Oops, sorry. I'm dropping this. I've started splitting it into several sub-commits. Thanks for the recommandations !

lib/Target/X86/X86SchedBroadwell.td

 // Loads, stores, and moves, not folded with other operations.
 defm : X86WriteRes<WriteLoad,    [BWPort23], 5, [1], 1>;
 defm : X86WriteRes<WriteStore,   [BWPort237, BWPort4], 1, [1,1], 1>;
 defm : X86WriteRes<WriteStoreNT, [BWPort237, BWPort4], 1, [1,1], 2>;
 defm : X86WriteRes<WriteMove,    [BWPort0156], 1, [1,1], 1>;
 
 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 // These can often bypass execution ports completely.
-def : WriteRes<WriteZero,  []>;
+def : WriteRes<WriteZero,    []> {
+  let Latency = 0;
+  let NumMicroOps = 0;
+}
 
 // Treat misc copies as a move.
 def : InstRW<[WriteMove], (instrs COPY)>;
 
 // Branches don't produce values, so they have no latency, but they still
 // consume resources. Indirect branches can fold loads.
 defm : BWWriteResPair<WriteJump,  [BWPort06],   1>;
 

lib/Target/X86/X86SchedHaswell.td

 def : WriteRes<WriteRMW, [HWPort237,HWPort4]>;
 
 // Store_addr on 237.
 // Store_data on 4.
 defm : X86WriteRes<WriteStore,   [HWPort237, HWPort4], 1, [1,1], 1>;
 defm : X86WriteRes<WriteStoreNT, [HWPort237, HWPort4], 1, [1,1], 2>;
 defm : X86WriteRes<WriteLoad,    [HWPort23], 5, [1], 1>;
 defm : X86WriteRes<WriteMove,    [HWPort0156], 1, [1], 1>;
-def  : WriteRes<WriteZero,       []>;
+def : WriteRes<WriteZero,    []> {
+  let Latency = 0;
+  let NumMicroOps = 0;
+}
 
 defm : HWWriteResPair<WriteALU,    [HWPort0156], 1>;
 defm : HWWriteResPair<WriteADC,    [HWPort06,HWPort0156], 2, [1,1], 2>;
 defm : HWWriteResPair<WriteIMul,   [HWPort1],   3>;
 defm : HWWriteResPair<WriteIMul64, [HWPort1],   3>;
 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
 defm : HWWriteResPair<WriteShift,  [HWPort06],  1>;
 defm : HWWriteResPair<WriteJump,   [HWPort06],  1>;

lib/Target/X86/X86SchedSandyBridge.td

 // A folded store needs a cycle on port 4 for the store data, and an extra port
 // 2/3 cycle to recompute the address.
 def : WriteRes<WriteRMW, [SBPort23,SBPort4]>;
 
 def : WriteRes<WriteStore,   [SBPort23, SBPort4]>;
 def : WriteRes<WriteStoreNT, [SBPort23, SBPort4]>;
 def : WriteRes<WriteLoad,    [SBPort23]> { let Latency = 5; }
 def : WriteRes<WriteMove,    [SBPort015]>;
-def : WriteRes<WriteZero,    []>;
+def : WriteRes<WriteZero,    []> {
+  let Latency = 0;
+  let NumMicroOps = 0;
+}
 
 defm : SBWriteResPair<WriteALU,    [SBPort015], 1>;
 defm : SBWriteResPair<WriteADC,    [SBPort05,SBPort015], 2, [1,1], 2>;
 defm : SBWriteResPair<WriteIMul,   [SBPort1],   3>;
 defm : SBWriteResPair<WriteIMul64, [SBPort1],   3>;
 
 defm : SBWriteResPair<WriteDiv8,   [SBPort0, SBDivider], 25, [1, 10]>;
 defm : SBWriteResPair<WriteDiv16,  [SBPort0, SBDivider], 25, [1, 10]>;

lib/Target/X86/X86SchedSkylakeClient.td

 // Loads, stores, and moves, not folded with other operations.
 defm : X86WriteRes<WriteLoad,    [SKLPort23], 5, [1], 1>;
 defm : X86WriteRes<WriteStore,   [SKLPort237, SKLPort4], 1, [1,1], 1>;
 defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>;
 defm : X86WriteRes<WriteMove,    [SKLPort0156], 1, [1], 1>;
 
 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 // These can often bypass execution ports completely.
-def : WriteRes<WriteZero,  []>;
+def : WriteRes<WriteZero,    []> {
+  let Latency = 0;
+  let NumMicroOps = 0;
+}
 
 // Branches don't produce values, so they have no latency, but they still
 // consume resources. Indirect branches can fold loads.
 defm : SKLWriteResPair<WriteJump,  [SKLPort06],   1>;
 
 // Floating point. This covers both scalar and vector operations.
 defm : X86WriteRes<WriteFLoad,         [SKLPort23], 5, [1], 1>;
 defm : X86WriteRes<WriteFLoadX,        [SKLPort23], 6, [1], 1>;

lib/Target/X86/X86SchedSkylakeServer.td

 // Loads, stores, and moves, not folded with other operations.
 defm : X86WriteRes<WriteLoad,    [SKXPort23], 5, [1], 1>;
 defm : X86WriteRes<WriteStore,   [SKXPort237, SKXPort4], 1, [1,1], 1>;
 defm : X86WriteRes<WriteStoreNT, [SKXPort237, SKXPort4], 1, [1,1], 2>;
 defm : X86WriteRes<WriteMove,    [SKXPort0156], 1, [1], 1>;
 
 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 // These can often bypass execution ports completely.
-def : WriteRes<WriteZero,  []>;
+def : WriteRes<WriteZero,    []> {
+  let Latency = 0;
+  let NumMicroOps = 0;
+}
 
 // Branches don't produce values, so they have no latency, but they still
 // consume resources. Indirect branches can fold loads.
 defm : SKXWriteResPair<WriteJump,  [SKXPort06],   1>;
 
 // Floating point. This covers both scalar and vector operations.
 defm : X86WriteRes<WriteFLoad,         [SKXPort23], 5, [1], 1>;
 defm : X86WriteRes<WriteFLoadX,        [SKXPort23], 6, [1], 1>;

lib/Target/X86/X86ScheduleAtom.td

 // Treat misc copies as a move.
 def : InstRW<[WriteMove], (instrs COPY)>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 // These can often bypass execution ports completely.
 ////////////////////////////////////////////////////////////////////////////////
 
-def : WriteRes<WriteZero,  []>;
+def : WriteRes<WriteZero,    []> {
+  let Latency = 0;
+  let NumMicroOps = 0;
+}
 
 ////////////////////////////////////////////////////////////////////////////////
 // Branches don't produce values, so they have no latency, but they still
 // consume resources. Indirect branches can fold loads.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : AtomWriteResPair<WriteJump, [AtomPort1], [AtomPort1]>;
 

lib/Target/X86/X86ScheduleBtVer2.td

 // Treat misc copies as a move.
 def : InstRW<[WriteMove], (instrs COPY)>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 // These can often bypass execution ports completely.
 ////////////////////////////////////////////////////////////////////////////////
 
-def : WriteRes<WriteZero,  []>;
+def : WriteRes<WriteZero,    []> {
+  let Latency = 0;
+  let NumMicroOps = 0;
+}
 
 ////////////////////////////////////////////////////////////////////////////////
 // Branches don't produce values, so they have no latency, but they still
 // consume resources. Indirect branches can fold loads.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : JWriteResIntPair<WriteJump,  [JALU01], 1>;
 

lib/Target/X86/X86ScheduleSLM.td

 // A folded store needs a cycle on MEC_RSV for the store data, but it does not
 // need an extra port cycle to recompute the address.
 def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;
 
 def : WriteRes<WriteStore,   [SLM_IEC_RSV01, SLM_MEC_RSV]>;
 def : WriteRes<WriteStoreNT, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
 def : WriteRes<WriteLoad,    [SLM_MEC_RSV]> { let Latency = 3; }
 def : WriteRes<WriteMove,    [SLM_IEC_RSV01]>;
-def : WriteRes<WriteZero,    []>;
+def : WriteRes<WriteZero,    []> {
+  let Latency = 0;
+  let NumMicroOps = 0;
+}
 
 // Load/store MXCSR.
 // FIXME: These are probably wrong. They are copy pasted from WriteStore/Load.
 def : WriteRes<WriteSTMXCSR, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
 def : WriteRes<WriteLDMXCSR,  [SLM_MEC_RSV]> { let Latency = 3; }
 
 // Treat misc copies as a move.
 def : InstRW<[WriteMove], (instrs COPY)>;

lib/Target/X86/X86ScheduleZnver1.td

 // operation in codegen
 def : WriteRes<WriteRMW, [ZnAGU]>;
 
 def : WriteRes<WriteStore,   [ZnAGU]>;
 def : WriteRes<WriteStoreNT, [ZnAGU]>;
 def : WriteRes<WriteMove,    [ZnALU]>;
 def : WriteRes<WriteLoad,    [ZnAGU]> { let Latency = 8; }
 
-def : WriteRes<WriteZero,  []>;
+def : WriteRes<WriteZero,    []> {
+  let Latency = 0;
+  let NumMicroOps = 0;
+}
 def : WriteRes<WriteLEA, [ZnALU]>;
 defm : ZnWriteResPair<WriteALU,   [ZnALU], 1>;
 defm : ZnWriteResPair<WriteADC,   [ZnALU], 1>;
 defm : ZnWriteResPair<WriteIMul,   [ZnALU1, ZnMultiplier], 4>;
 defm : ZnWriteResPair<WriteIMul64, [ZnALU1, ZnMultiplier], 4, [1,1], 2>;
 defm : ZnWriteResPair<WriteShift, [ZnALU], 1>;
 defm : ZnWriteResPair<WriteJump,  [ZnALU], 1>;
 defm : ZnWriteResFpuPair<WriteCRC32, [ZnFPU0], 3>;

test/CodeGen/X86/avx512-intrinsics-upgrade.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
 
 declare i16 @llvm.x86.avx512.kunpck.bw(i16, i16) nounwind readnone
 
 define i16 @unpckbw_test(i16 %a0, i16 %a1) {
 ; CHECK-LABEL: unpckbw_test:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    kmovw %edi, %k0
 ; CHECK-NEXT:    kmovw %esi, %k1

 define <8 x i16> @test_cmp_d_512(<16 x i32> %a0, <16 x i32> %a1) {
 ; CHECK-LABEL: test_cmp_d_512:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    vpcmpeqd %zmm1, %zmm0, %k0
 ; CHECK-NEXT:    vpcmpgtd %zmm0, %zmm1, %k1
 ; CHECK-NEXT:    vpcmpled %zmm1, %zmm0, %k2
 ; CHECK-NEXT:    vpcmpneqd %zmm1, %zmm0, %k3
 ; CHECK-NEXT:    vpcmpnltd %zmm1, %zmm0, %k4
-; CHECK-NEXT:    vpcmpgtd %zmm1, %zmm0, %k5
 ; CHECK-NEXT:    kmovw %k0, %eax
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; CHECK-NEXT:    vpinsrw $0, %eax, %xmm0, %xmm0
+; CHECK-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vpinsrw $0, %eax, %xmm2, %xmm2
 ; CHECK-NEXT:    kmovw %k1, %eax
-; CHECK-NEXT:    vpinsrw $1, %eax, %xmm0, %xmm0
+; CHECK-NEXT:    vpinsrw $1, %eax, %xmm2, %xmm2
 ; CHECK-NEXT:    kmovw %k2, %eax
-; CHECK-NEXT:    vpinsrw $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT:    vpinsrw $2, %eax, %xmm2, %xmm2
 ; CHECK-NEXT:    kmovw %k3, %eax
-; CHECK-NEXT:    vpinsrw $4, %eax, %xmm0, %xmm0
+; CHECK-NEXT:    vpinsrw $4, %eax, %xmm2, %xmm2
 ; CHECK-NEXT:    kmovw %k4, %eax
-; CHECK-NEXT:    vpinsrw $5, %eax, %xmm0, %xmm0
-; CHECK-NEXT:    kmovw %k5, %eax
-; CHECK-NEXT:    vpinsrw $6, %eax, %xmm0, %xmm0
+; CHECK-NEXT:    vpinsrw $5, %eax, %xmm2, %xmm2
+; CHECK-NEXT:    vpcmpgtd %zmm1, %zmm0, %k0
+; CHECK-NEXT:    kmovw %k0, %eax
+; CHECK-NEXT:    vpinsrw $6, %eax, %xmm2, %xmm0
 ; CHECK-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
 ; CHECK-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
 ; CHECK-NEXT:    retq
   %res0 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 0, i16 -1)
   %vec0 = insertelement <8 x i16> undef, i16 %res0, i32 0
   %res1 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 1, i16 -1)
   %vec1 = insertelement <8 x i16> %vec0, i16 %res1, i32 1
   %res2 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 2, i16 -1)

 define <8 x i16> @test_ucmp_d_512(<16 x i32> %a0, <16 x i32> %a1) {
 ; CHECK-LABEL: test_ucmp_d_512:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    vpcmpeqd %zmm1, %zmm0, %k0
 ; CHECK-NEXT:    vpcmpltud %zmm1, %zmm0, %k1
 ; CHECK-NEXT:    vpcmpleud %zmm1, %zmm0, %k2
 ; CHECK-NEXT:    vpcmpneqd %zmm1, %zmm0, %k3
 ; CHECK-NEXT:    vpcmpnltud %zmm1, %zmm0, %k4
-; CHECK-NEXT:    vpcmpnleud %zmm1, %zmm0, %k5
 ; CHECK-NEXT:    kmovw %k0, %eax
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
-; CHECK-NEXT:    vpinsrw $0, %eax, %xmm0, %xmm0
+; CHECK-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vpinsrw $0, %eax, %xmm2, %xmm2
 ; CHECK-NEXT:    kmovw %k1, %eax
-; CHECK-NEXT:    vpinsrw $1, %eax, %xmm0, %xmm0
+; CHECK-NEXT:    vpinsrw $1, %eax, %xmm2, %xmm2
 ; CHECK-NEXT:    kmovw %k2, %eax
-; CHECK-NEXT:    vpinsrw $2, %eax, %xmm0, %xmm0
+; CHECK-NEXT:    vpinsrw $2, %eax, %xmm2, %xmm2
 ; CHECK-NEXT:    kmovw %k3, %eax
-; CHECK-NEXT:    vpinsrw $4, %eax, %xmm0, %xmm0
+; CHECK-NEXT:    vpinsrw $4, %eax, %xmm2, %xmm2
 ; CHECK-NEXT:    kmovw %k4, %eax
-; CHECK-NEXT:    vpinsrw $5, %eax, %xmm0, %xmm0
-; CHECK-NEXT:    kmovw %k5, %eax
-; CHECK-NEXT:    vpinsrw $6, %eax, %xmm0, %xmm0
+; CHECK-NEXT:    vpinsrw $5, %eax, %xmm2, %xmm2
+; CHECK-NEXT:    vpcmpnleud %zmm1, %zmm0, %k0
+; CHECK-NEXT:    kmovw %k0, %eax
+; CHECK-NEXT:    vpinsrw $6, %eax, %xmm2, %xmm0
 ; CHECK-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
 ; CHECK-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
 ; CHECK-NEXT:    retq
   %res0 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 0, i16 -1)
   %vec0 = insertelement <8 x i16> undef, i16 %res0, i32 0
   %res1 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 1, i16 -1)
   %vec1 = insertelement <8 x i16> %vec0, i16 %res1, i32 1
   %res2 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 2, i16 -1)

test/CodeGen/X86/avx512vl-intrinsics.ll

 ; CHECK-NEXT:    movq _xmm@{{.*}}(%rip), %rax ## encoding: [0x48,0x8b,0x05,A,A,A,A]
 ; CHECK-NEXT:    ## fixup A - offset: 3, value: _xmm@GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
 ; CHECK-NEXT:    vmovdqa (%rax), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0x00]
 ; CHECK-NEXT:    movq _k8@{{.*}}(%rip), %rax ## encoding: [0x48,0x8b,0x05,A,A,A,A]
 ; CHECK-NEXT:    ## fixup A - offset: 3, value: _k8@GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
 ; CHECK-NEXT:    movzbl (%rax), %eax ## encoding: [0x0f,0xb6,0x00]
 ; CHECK-NEXT:    kmovw %eax, %k1 ## encoding: [0xc5,0xf8,0x92,0xc8]
 ; CHECK-NEXT:    vpcompressd %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0x89,0x8b,0xc0]
+; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0xef,0xc9]
 ; CHECK-NEXT:    vmovdqa %xmm0, -{{[0-9]+}}(%rsp) ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x7f,0x44,0x24,0xd8]
-; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0]
-; CHECK-NEXT:    vmovdqa %xmm0, -{{[0-9]+}}(%rsp) ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x7f,0x44,0x24,0xe8]
+; CHECK-NEXT:    vmovdqa %xmm1, -{{[0-9]+}}(%rsp) ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x7f,0x4c,0x24,0xe8]
 ; CHECK-NEXT:    xorl %eax, %eax ## encoding: [0x31,0xc0]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
 entry:
   %.compoundliteral = alloca <2 x i64>, align 16
   %res = alloca <4 x i32>, align 16
   %a0 = load <4 x i32>, <4 x i32>* @xmm, align 16
   %a2 = load i8, i8* @k8, align 1
   %a21 = call <4 x i32> @llvm.x86.avx512.mask.compress.d.128(<4 x i32> %a0, <4 x i32> zeroinitializer, i8 %a2) #2

test/CodeGen/X86/schedule-x86_64.ll

; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "cbw \0A\09 cdq \0A\09 cdqe \0A\09 cqo \0A\09 cwd \0A\09 cwde", ""() nounwind
   ret void
 }
 
 define void @test_clc_cld_cmc() optsize {
 ; GENERIC-LABEL: test_clc_cld_cmc:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    #APP
-; GENERIC-NEXT:    clc # sched: [1:?]
+; GENERIC-NEXT:    clc # sched: [0:?]
 ; GENERIC-NEXT:    cld # sched: [1:0.33]
 ; GENERIC-NEXT:    cmc # sched: [1:0.33]
 ; GENERIC-NEXT:    #NO_APP
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
 ; ATOM-LABEL: test_clc_cld_cmc:
 ; ATOM:       # %bb.0:
 ; ATOM-NEXT:    #APP

 ; SLM-NEXT:    cld # sched: [1:0.50]
 ; SLM-NEXT:    cmc # sched: [1:0.50]
 ; SLM-NEXT:    #NO_APP
 ; SLM-NEXT:    retq # sched: [4:1.00]
 ;
 ; SANDY-LABEL: test_clc_cld_cmc:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
-; SANDY-NEXT:    clc # sched: [1:?]
+; SANDY-NEXT:    clc # sched: [0:?]
 ; SANDY-NEXT:    cld # sched: [1:0.33]
 ; SANDY-NEXT:    cmc # sched: [1:0.33]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retq # sched: [1:1.00]
 ;
 ; HASWELL-LABEL: test_clc_cld_cmc:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    clc # sched: [1:?]
+; HASWELL-NEXT:    clc # sched: [0:?]
 ; HASWELL-NEXT:    cld # sched: [3:1.00]
 ; HASWELL-NEXT:    cmc # sched: [1:0.25]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retq # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_clc_cld_cmc:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
-; BROADWELL-NEXT:    clc # sched: [1:?]
+; BROADWELL-NEXT:    clc # sched: [0:?]
 ; BROADWELL-NEXT:    cld # sched: [3:1.00]
 ; BROADWELL-NEXT:    cmc # sched: [1:0.25]
 ; BROADWELL-NEXT:    #NO_APP
 ; BROADWELL-NEXT:    retq # sched: [7:1.00]
 ;
 ; SKYLAKE-LABEL: test_clc_cld_cmc:
 ; SKYLAKE:       # %bb.0:
 ; SKYLAKE-NEXT:    #APP
-; SKYLAKE-NEXT:    clc # sched: [1:?]
+; SKYLAKE-NEXT:    clc # sched: [0:?]
 ; SKYLAKE-NEXT:    cld # sched: [3:1.00]
 ; SKYLAKE-NEXT:    cmc # sched: [1:0.25]
 ; SKYLAKE-NEXT:    #NO_APP
 ; SKYLAKE-NEXT:    retq # sched: [7:1.00]
 ;
 ; SKX-LABEL: test_clc_cld_cmc:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    #APP
-; SKX-NEXT:    clc # sched: [1:?]
+; SKX-NEXT:    clc # sched: [0:?]
 ; SKX-NEXT:    cld # sched: [3:1.00]
 ; SKX-NEXT:    cmc # sched: [1:0.25]
 ; SKX-NEXT:    #NO_APP
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_clc_cld_cmc:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    #APP

test/CodeGen/X86/sttni.ll

 define void @pcmpistr_mask_index_flag(<16 x i8> %lhs, <16 x i8> %rhs, <16 x i8>* %mptr, i32* %iptr, i32* %fptr) nounwind {
 ; X32-LABEL: pcmpistr_mask_index_flag:
 ; X32:       # %bb.0: # %entry
 ; X32-NEXT:    pushl %ebx
 ; X32-NEXT:    pushl %esi
 ; X32-NEXT:    movdqa %xmm0, %xmm2
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; X32-NEXT:    pcmpistrm $24, %xmm1, %xmm0
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; X32-NEXT:    xorl %ebx, %ebx
 ; X32-NEXT:    pcmpistri $24, %xmm1, %xmm2
 ; X32-NEXT:    setb %bl
 ; X32-NEXT:    movdqa %xmm0, (%esi)
 ; X32-NEXT:    movl %ecx, (%edx)
 ; X32-NEXT:    movl %ebx, (%eax)
 ; X32-NEXT:    popl %esi
 ; X32-NEXT:    popl %ebx

 define void @pcmpistr_mask_index_flag_load(<16 x i8> %lhs, <16 x i8>* %rhsptr, <16 x i8>* %mptr, i32* %iptr, i32* %fptr) nounwind {
 ; X32-LABEL: pcmpistr_mask_index_flag_load:
 ; X32:       # %bb.0: # %entry
 ; X32-NEXT:    pushl %ebx
 ; X32-NEXT:    pushl %esi
 ; X32-NEXT:    movdqa %xmm0, %xmm1
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movdqu (%ecx), %xmm2
 ; X32-NEXT:    pcmpistrm $24, %xmm2, %xmm0
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; X32-NEXT:    xorl %ebx, %ebx
 ; X32-NEXT:    pcmpistri $24, %xmm2, %xmm1
 ; X32-NEXT:    setb %bl
 ; X32-NEXT:    movdqa %xmm0, (%esi)
 ; X32-NEXT:    movl %ecx, (%edx)
 ; X32-NEXT:    movl %ebx, (%eax)
 ; X32-NEXT:    popl %esi
 ; X32-NEXT:    popl %ebx
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: pcmpistr_mask_index_flag_load:
 ; X64:       # %bb.0: # %entry
-; X64-NEXT:    movq %rcx, %rax
 ; X64-NEXT:    movdqa %xmm0, %xmm1
 ; X64-NEXT:    movdqu (%rdi), %xmm2
 ; X64-NEXT:    pcmpistrm $24, %xmm2, %xmm0
+; X64-NEXT:    movq %rcx, %rax
 ; X64-NEXT:    xorl %edi, %edi
 ; X64-NEXT:    pcmpistri $24, %xmm2, %xmm1
 ; X64-NEXT:    setb %dil
 ; X64-NEXT:    movdqa %xmm0, (%rsi)
 ; X64-NEXT:    movl %ecx, (%rdx)
 ; X64-NEXT:    movl %edi, (%rax)
 ; X64-NEXT:    retq
 entry:

test/CodeGen/X86/vec_cast.ll

 ; CHECK-LIN-NEXT:    pinsrw $1, %esi, %xmm0
 ; CHECK-LIN-NEXT:    pinsrw $2, %edx, %xmm0
 ; CHECK-LIN-NEXT:    pxor %xmm1, %xmm1
 ; CHECK-LIN-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; CHECK-LIN-NEXT:    retq
 ;
 ; CHECK-WIN-LABEL: e:
 ; CHECK-WIN:       # %bb.0:
-; CHECK-WIN-NEXT:    # kill: def $r8w killed $r8w def $r8d
 ; CHECK-WIN-NEXT:    # kill: def $dx killed $dx def $edx
 ; CHECK-WIN-NEXT:    # kill: def $cx killed $cx def $ecx
 ; CHECK-WIN-NEXT:    movd %ecx, %xmm0
 ; CHECK-WIN-NEXT:    pinsrw $1, %edx, %xmm0
+; CHECK-WIN-NEXT:    # kill: def $r8w killed $r8w def $r8d
 ; CHECK-WIN-NEXT:    pinsrw $2, %r8d, %xmm0
 ; CHECK-WIN-NEXT:    pxor %xmm1, %xmm1
 ; CHECK-WIN-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; CHECK-WIN-NEXT:    retq
   %c = zext <3 x i16> %a to <3 x i32>
   ret <3 x i32> %c
 }
 

test/CodeGen/X86/x87-schedule.ll

 ; ATOM-NEXT:    fldpi # sched: [10:5.00]
 ; ATOM-NEXT:    fldz # sched: [1:0.50]
 ; ATOM-NEXT:    #NO_APP
 ; ATOM-NEXT:    retl # sched: [79:39.50]
 ;
 ; SLM-LABEL: test_fld1_fldl2e_fldl2t_fldlg2_fldln2_fldpi_fldz:
 ; SLM:       # %bb.0:
 ; SLM-NEXT:    #APP
-; SLM-NEXT:    fld1 # sched: [1:?]
+; SLM-NEXT:    fld1 # sched: [0:?]
 ; SLM-NEXT:    fldl2e # sched: [100:1.00]
 ; SLM-NEXT:    fldl2t # sched: [100:1.00]
 ; SLM-NEXT:    fldlg2 # sched: [100:1.00]
 ; SLM-NEXT:    fldln2 # sched: [100:1.00]
 ; SLM-NEXT:    fldpi # sched: [100:1.00]
-; SLM-NEXT:    fldz # sched: [1:?]
+; SLM-NEXT:    fldz # sched: [0:?]
 ; SLM-NEXT:    #NO_APP
 ; SLM-NEXT:    retl # sched: [4:1.00]
 ;
 ; SANDY-LABEL: test_fld1_fldl2e_fldl2t_fldlg2_fldln2_fldpi_fldz:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
-; SANDY-NEXT:    fld1 # sched: [1:?]
+; SANDY-NEXT:    fld1 # sched: [0:?]
 ; SANDY-NEXT:    fldl2e # sched: [100:0.33]
 ; SANDY-NEXT:    fldl2t # sched: [100:0.33]
 ; SANDY-NEXT:    fldlg2 # sched: [100:0.33]
 ; SANDY-NEXT:    fldln2 # sched: [100:0.33]
 ; SANDY-NEXT:    fldpi # sched: [100:0.33]
-; SANDY-NEXT:    fldz # sched: [1:?]
+; SANDY-NEXT:    fldz # sched: [0:?]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retl # sched: [6:1.00]
 ;
 ; HASWELL-LABEL: test_fld1_fldl2e_fldl2t_fldlg2_fldln2_fldpi_fldz:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
-; HASWELL-NEXT:    fld1 # sched: [1:?]
+; HASWELL-NEXT:    fld1 # sched: [0:?]
 ; HASWELL-NEXT:    fldl2e # sched: [1:0.50]
 ; HASWELL-NEXT:    fldl2t # sched: [1:0.50]
 ; HASWELL-NEXT:    fldlg2 # sched: [1:0.50]
 ; HASWELL-NEXT:    fldln2 # sched: [1:0.50]
 ; HASWELL-NEXT:    fldpi # sched: [1:0.50]
 ; HASWELL-NEXT:    fldz # sched: [1:0.50]
 ; HASWELL-NEXT:    #NO_APP
 ; HASWELL-NEXT:    retl # sched: [7:1.00]
 ;
 ; BROADWELL-LABEL: test_fld1_fldl2e_fldl2t_fldlg2_fldln2_fldpi_fldz:
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
-; BROADWELL-NEXT:    fld1 # sched: [1:?]
+; BROADWELL-NEXT:    fld1 # sched: [0:?]
 ; BROADWELL-NEXT:    fldl2e # sched: [100:0.25]
 ; BROADWELL-NEXT:    fldl2t # sched: [100:0.25]
 ; BROADWELL-NEXT:    fldlg2 # sched: [100:0.25]
 ; BROADWELL-NEXT:    fldln2 # sched: [100:0.25]
 ; BROADWELL-NEXT:    fldpi # sched: [100:0.25]
-; BROADWELL-NEXT:    fldz # sched: [1:?]
+; BROADWELL-NEXT:    fldz # sched: [0:?]
 ; BROADWELL-NEXT:    #NO_APP
 ; BROADWELL-NEXT:    retl # sched: [6:0.50]
 ;
 ; SKYLAKE-LABEL: test_fld1_fldl2e_fldl2t_fldlg2_fldln2_fldpi_fldz:
 ; SKYLAKE:       # %bb.0:
 ; SKYLAKE-NEXT:    #APP
-; SKYLAKE-NEXT:    fld1 # sched: [1:?]
+; SKYLAKE-NEXT:    fld1 # sched: [0:?]
 ; SKYLAKE-NEXT:    fldl2e # sched: [100:0.25]
 ; SKYLAKE-NEXT:    fldl2t # sched: [100:0.25]
 ; SKYLAKE-NEXT:    fldlg2 # sched: [100:0.25]
 ; SKYLAKE-NEXT:    fldln2 # sched: [100:0.25]
 ; SKYLAKE-NEXT:    fldpi # sched: [100:0.25]
-; SKYLAKE-NEXT:    fldz # sched: [1:?]
+; SKYLAKE-NEXT:    fldz # sched: [0:?]
 ; SKYLAKE-NEXT:    #NO_APP
 ; SKYLAKE-NEXT:    retl # sched: [6:0.50]
 ;
 ; SKX-LABEL: test_fld1_fldl2e_fldl2t_fldlg2_fldln2_fldpi_fldz:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    #APP
-; SKX-NEXT:    fld1 # sched: [1:?]
+; SKX-NEXT:    fld1 # sched: [0:?]
 ; SKX-NEXT:    fldl2e # sched: [100:0.25]
 ; SKX-NEXT:    fldl2t # sched: [100:0.25]
 ; SKX-NEXT:    fldlg2 # sched: [100:0.25]
 ; SKX-NEXT:    fldln2 # sched: [100:0.25]
 ; SKX-NEXT:    fldpi # sched: [100:0.25]
-; SKX-NEXT:    fldz # sched: [1:?]
+; SKX-NEXT:    fldz # sched: [0:?]
 ; SKX-NEXT:    #NO_APP
 ; SKX-NEXT:    retl # sched: [6:0.50]
 ;
 ; BTVER2-LABEL: test_fld1_fldl2e_fldl2t_fldlg2_fldln2_fldpi_fldz:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    fld1 # sched: [1:?]
+; BTVER2-NEXT:    fld1 # sched: [0:?]
 ; BTVER2-NEXT:    fldl2e # sched: [100:0.50]
 ; BTVER2-NEXT:    fldl2t # sched: [100:0.50]
 ; BTVER2-NEXT:    fldlg2 # sched: [100:0.50]
 ; BTVER2-NEXT:    fldln2 # sched: [100:0.50]
 ; BTVER2-NEXT:    fldpi # sched: [100:0.50]
-; BTVER2-NEXT:    fldz # sched: [1:?]
+; BTVER2-NEXT:    fldz # sched: [0:?]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fld1_fldl2e_fldl2t_fldlg2_fldln2_fldpi_fldz:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    fld1 # sched: [11:1.00]
 ; ZNVER1-NEXT:    fldl2e # sched: [11:1.00]

test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll

 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: testCmpZero:
 ; X32:       # %bb.0: # %entry
 ; X32-NEXT:    pushl %ebx
 ; X32-NEXT:    pushl %esi
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    addl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X32-NEXT:    addl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    addl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    xorl %esi, %esi
 ; X32-NEXT:    .p2align 4, 0x90
 ; X32-NEXT:  .LBB5_1: # %for.body82.us
 ; X32-NEXT:    # =>This Inner Loop Header: Depth=1
-; X32-NEXT:    movzbl (%edx,%esi,4), %ebx
-; X32-NEXT:    movb %bl, (%ecx,%esi)
+; X32-NEXT:    movzbl (%ecx,%esi,4), %ebx
+; X32-NEXT:    movb %bl, (%edx,%esi)
 ; X32-NEXT:    incl %esi
 ; X32-NEXT:    cmpl %esi, %eax
 ; X32-NEXT:    jne .LBB5_1
 ; X32-NEXT:  # %bb.2: # %return
 ; X32-NEXT:    popl %esi
 ; X32-NEXT:    popl %ebx
 ; X32-NEXT:    retl
 entry:

test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s

 # CHECK-NEXT:  1      1     0.50                        btq $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btcq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btrq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btsq  $7, %rdi
 # CHECK-NEXT:  2      6     0.50    *                   btq $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btcq  $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btrq  $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btsq  $7, (%rax)
-# CHECK-NEXT:  1      1      -                    *     clc
+# CHECK-NEXT:  0      0      -                    *     clc
 # CHECK-NEXT:  1      1     0.25                        decb  %dil
 # CHECK-NEXT:  3      7     1.00    *      *            decb  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decw  %di
 # CHECK-NEXT:  3      7     1.00    *      *            decw  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decl  %edi
 # CHECK-NEXT:  3      7     1.00    *      *            decl  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decq  %rdi
 # CHECK-NEXT:  3      7     1.00    *      *            decq  (%rax)

test/tools/llvm-mca/X86/Broadwell/resources-x87.s

 # CHECK-NEXT:  3      4     1.00           *      *     fisttpl (%ecx)
 # CHECK-NEXT:  3      4     1.00           *      *     fisttpll  (%eax)
 # CHECK-NEXT:  1      1     0.25                  *     fld %st(0)
 # CHECK-NEXT:  1      6     0.50    *             *     flds  (%edx)
 # CHECK-NEXT:  1      6     0.50    *             *     fldl  (%ecx)
 # CHECK-NEXT:  1      6     0.50    *             *     fldt  (%eax)
 # CHECK-NEXT:  3      7     1.00    *             *     fldcw (%eax)
 # CHECK-NEXT:  64     60    14.00                 *     fldenv  (%eax)
-# CHECK-NEXT:  1      1      -                    *     fld1
+# CHECK-NEXT:  0      0      -                    *     fld1
 # CHECK-NEXT:  1      100   0.25                  *     fldl2e
 # CHECK-NEXT:  1      100   0.25                  *     fldl2t
 # CHECK-NEXT:  1      100   0.25                  *     fldlg2
 # CHECK-NEXT:  1      100   0.25                  *     fldln2
 # CHECK-NEXT:  1      100   0.25                  *     fldpi
-# CHECK-NEXT:  1      1      -                    *     fldz
+# CHECK-NEXT:  0      0      -                    *     fldz
 # CHECK-NEXT:  1      5     1.00                  *     fmul  %st(0), %st(1)
 # CHECK-NEXT:  1      5     1.00                  *     fmul  %st(2)
 # CHECK-NEXT:  2      11    1.00    *             *     fmuls (%ecx)
 # CHECK-NEXT:  2      11    1.00    *             *     fmull (%eax)
 # CHECK-NEXT:  1      5     1.00                  *     fmulp %st(1)
 # CHECK-NEXT:  1      5     1.00                  *     fmulp %st(2)
 # CHECK-NEXT:  3      14    1.00    *             *     fimuls  (%ecx)
 # CHECK-NEXT:  3      14    1.00    *             *     fimull  (%eax)

test/tools/llvm-mca/X86/BtVer2/resources-x87.s

 # CHECK-NEXT:  1      1     1.00           *      *     fisttpl (%ecx)
 # CHECK-NEXT:  1      1     1.00           *      *     fisttpll  (%eax)
 # CHECK-NEXT:  1      1     0.50                  *     fld %st(0)
 # CHECK-NEXT:  1      5     1.00    *             *     flds  (%edx)
 # CHECK-NEXT:  1      5     1.00    *             *     fldl  (%ecx)
 # CHECK-NEXT:  1      5     1.00    *             *     fldt  (%eax)
 # CHECK-NEXT:  1      5     1.00    *             *     fldcw (%eax)
 # CHECK-NEXT:  1      100   0.50                  *     fldenv  (%eax)
-# CHECK-NEXT:  1      1      -                    *     fld1
+# CHECK-NEXT:  0      0      -                    *     fld1
 # CHECK-NEXT:  1      100   0.50                  *     fldl2e
 # CHECK-NEXT:  1      100   0.50                  *     fldl2t
 # CHECK-NEXT:  1      100   0.50                  *     fldlg2
 # CHECK-NEXT:  1      100   0.50                  *     fldln2
 # CHECK-NEXT:  1      100   0.50                  *     fldpi
-# CHECK-NEXT:  1      1      -                    *     fldz
+# CHECK-NEXT:  0      0      -                    *     fldz
 # CHECK-NEXT:  1      2     1.00                  *     fmul  %st(0), %st(1)
 # CHECK-NEXT:  1      2     1.00                  *     fmul  %st(2)
 # CHECK-NEXT:  1      7     1.00    *             *     fmuls (%ecx)
 # CHECK-NEXT:  1      7     1.00    *             *     fmull (%eax)
 # CHECK-NEXT:  1      2     1.00                  *     fmulp %st(1)
 # CHECK-NEXT:  1      2     1.00                  *     fmulp %st(2)
 # CHECK-NEXT:  1      7     1.00    *             *     fimuls  (%ecx)
 # CHECK-NEXT:  1      7     1.00    *             *     fimull  (%eax)

test/tools/llvm-mca/X86/Haswell/resources-x86_64.s

 # CHECK-NEXT:  1      1     0.50                        btq $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btcq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btrq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btsq  $7, %rdi
 # CHECK-NEXT:  2      6     0.50    *                   btq $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btcq  $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btrq  $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btsq  $7, (%rax)
-# CHECK-NEXT:  1      1      -                    *     clc
+# CHECK-NEXT:  0      0      -                    *     clc
 # CHECK-NEXT:  1      1     0.25                        decb  %dil
 # CHECK-NEXT:  3      7     1.00    *      *            decb  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decw  %di
 # CHECK-NEXT:  3      7     1.00    *      *            decw  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decl  %edi
 # CHECK-NEXT:  3      7     1.00    *      *            decl  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decq  %rdi
 # CHECK-NEXT:  3      7     1.00    *      *            decq  (%rax)

test/tools/llvm-mca/X86/Haswell/resources-x87.s

 # CHECK-NEXT:  3      4     1.00           *      *     fisttpl (%ecx)
 # CHECK-NEXT:  3      4     1.00           *      *     fisttpll  (%eax)
 # CHECK-NEXT:  1      1     0.50                  *     fld %st(0)
 # CHECK-NEXT:  1      7     0.50    *             *     flds  (%edx)
 # CHECK-NEXT:  1      7     0.50    *             *     fldl  (%ecx)
 # CHECK-NEXT:  1      7     0.50    *             *     fldt  (%eax)
 # CHECK-NEXT:  3      7     1.00    *             *     fldcw (%eax)
 # CHECK-NEXT:  64     61    14.00                 *     fldenv  (%eax)
-# CHECK-NEXT:  1      1      -                    *     fld1
+# CHECK-NEXT:  0      0      -                    *     fld1
 # CHECK-NEXT:  2      1     0.50                  *     fldl2e
 # CHECK-NEXT:  2      1     0.50                  *     fldl2t
 # CHECK-NEXT:  2      1     0.50                  *     fldlg2
 # CHECK-NEXT:  2      1     0.50                  *     fldln2
 # CHECK-NEXT:  2      1     0.50                  *     fldpi
 # CHECK-NEXT:  1      1     0.50                  *     fldz
 # CHECK-NEXT:  1      5     1.00                  *     fmul  %st(0), %st(1)
 # CHECK-NEXT:  1      5     1.00                  *     fmul  %st(2)

test/tools/llvm-mca/X86/SLM/resources-x87.s

 # CHECK-NEXT:  1      1     1.00           *      *     fisttpl (%ecx)
 # CHECK-NEXT:  1      1     1.00           *      *     fisttpll  (%eax)
 # CHECK-NEXT:  1      1     0.50                  *     fld %st(0)
 # CHECK-NEXT:  1      3     1.00    *             *     flds  (%edx)
 # CHECK-NEXT:  1      3     1.00    *             *     fldl  (%ecx)
 # CHECK-NEXT:  1      3     1.00    *             *     fldt  (%eax)
 # CHECK-NEXT:  1      3     1.00    *             *     fldcw (%eax)
 # CHECK-NEXT:  1      100   1.00                  *     fldenv  (%eax)
-# CHECK-NEXT:  1      1      -                    *     fld1
+# CHECK-NEXT:  0      0      -                    *     fld1
 # CHECK-NEXT:  1      100   1.00                  *     fldl2e
 # CHECK-NEXT:  1      100   1.00                  *     fldl2t
 # CHECK-NEXT:  1      100   1.00                  *     fldlg2
 # CHECK-NEXT:  1      100   1.00                  *     fldln2
 # CHECK-NEXT:  1      100   1.00                  *     fldpi
-# CHECK-NEXT:  1      1      -                    *     fldz
+# CHECK-NEXT:  0      0      -                    *     fldz
 # CHECK-NEXT:  1      5     2.00                  *     fmul  %st(0), %st(1)
 # CHECK-NEXT:  1      5     2.00                  *     fmul  %st(2)
 # CHECK-NEXT:  1      8     2.00    *             *     fmuls (%ecx)
 # CHECK-NEXT:  1      8     2.00    *             *     fmull (%eax)
 # CHECK-NEXT:  1      5     2.00                  *     fmulp %st(1)
 # CHECK-NEXT:  1      5     2.00                  *     fmulp %st(2)
 # CHECK-NEXT:  1      8     2.00    *             *     fimuls  (%ecx)
 # CHECK-NEXT:  1      8     2.00    *             *     fimull  (%eax)

test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s

 # CHECK-NEXT:  1      1     0.50                        btq $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btcq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btrq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btsq  $7, %rdi
 # CHECK-NEXT:  2      6     0.50    *                   btq $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btcq  $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btrq  $7, (%rax)
 # CHECK-NEXT:  4      7     1.00    *      *            btsq  $7, (%rax)
-# CHECK-NEXT:  1      1      -                    *     clc
+# CHECK-NEXT:  0      0      -                    *     clc
 # CHECK-NEXT:  1      1     0.33                        decb  %dil
 # CHECK-NEXT:  3      7     1.00    *      *            decb  (%rax)
 # CHECK-NEXT:  1      1     0.33                        decw  %di
 # CHECK-NEXT:  3      7     1.00    *      *            decw  (%rax)
 # CHECK-NEXT:  1      1     0.33                        decl  %edi
 # CHECK-NEXT:  3      7     1.00    *      *            decl  (%rax)
 # CHECK-NEXT:  1      1     0.33                        decq  %rdi
 # CHECK-NEXT:  3      7     1.00    *      *            decq  (%rax)

test/tools/llvm-mca/X86/SandyBridge/resources-x87.s

 # CHECK-NEXT:  3      5     1.00           *      *     fisttpl (%ecx)
 # CHECK-NEXT:  3      5     1.00           *      *     fisttpll  (%eax)
 # CHECK-NEXT:  1      1     1.00                  *     fld %st(0)
 # CHECK-NEXT:  3      9     1.00    *             *     flds  (%edx)
 # CHECK-NEXT:  3      9     1.00    *             *     fldl  (%ecx)
 # CHECK-NEXT:  3      9     1.00    *             *     fldt  (%eax)
 # CHECK-NEXT:  5      8     2.00    *             *     fldcw (%eax)
 # CHECK-NEXT:  1      100   0.33                  *     fldenv  (%eax)
-# CHECK-NEXT:  1      1      -                    *     fld1
+# CHECK-NEXT:  0      0      -                    *     fld1
 # CHECK-NEXT:  1      100   0.33                  *     fldl2e
 # CHECK-NEXT:  1      100   0.33                  *     fldl2t
 # CHECK-NEXT:  1      100   0.33                  *     fldlg2
 # CHECK-NEXT:  1      100   0.33                  *     fldln2
 # CHECK-NEXT:  1      100   0.33                  *     fldpi
-# CHECK-NEXT:  1      1      -                    *     fldz
+# CHECK-NEXT:  0      0      -                    *     fldz
 # CHECK-NEXT:  1      5     1.00                  *     fmul  %st(0), %st(1)
 # CHECK-NEXT:  1      5     1.00                  *     fmul  %st(2)
 # CHECK-NEXT:  2      12    1.00    *             *     fmuls (%ecx)
 # CHECK-NEXT:  2      12    1.00    *             *     fmull (%eax)
 # CHECK-NEXT:  1      5     1.00                  *     fmulp %st(1)
 # CHECK-NEXT:  1      5     1.00                  *     fmulp %st(2)
 # CHECK-NEXT:  3      15    1.00    *             *     fimuls  (%ecx)
 # CHECK-NEXT:  3      15    1.00    *             *     fimull  (%eax)

test/tools/llvm-mca/X86/SkylakeClient/resources-x86_64.s

 # CHECK-NEXT:  1      1     0.50                        btq $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btcq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btrq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btsq  $7, %rdi
 # CHECK-NEXT:  2      6     0.50    *                   btq $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btcq  $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btrq  $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btsq  $7, (%rax)
-# CHECK-NEXT:  1      1      -                    *     clc
+# CHECK-NEXT:  0      0      -                    *     clc
 # CHECK-NEXT:  1      1     0.25                        decb  %dil
 # CHECK-NEXT:  3      7     1.00    *      *            decb  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decw  %di
 # CHECK-NEXT:  3      7     1.00    *      *            decw  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decl  %edi
 # CHECK-NEXT:  3      7     1.00    *      *            decl  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decq  %rdi
 # CHECK-NEXT:  3      7     1.00    *      *            decq  (%rax)

test/tools/llvm-mca/X86/SkylakeClient/resources-x87.s

 # CHECK-NEXT:  3      4     1.00           *      *     fisttpl (%ecx)
 # CHECK-NEXT:  3      4     1.00           *      *     fisttpll  (%eax)
 # CHECK-NEXT:  1      1     0.25                  *     fld %st(0)
 # CHECK-NEXT:  1      7     0.50    *             *     flds  (%edx)
 # CHECK-NEXT:  1      7     0.50    *             *     fldl  (%ecx)
 # CHECK-NEXT:  1      7     0.50    *             *     fldt  (%eax)
 # CHECK-NEXT:  3      7     1.00    *             *     fldcw (%eax)
 # CHECK-NEXT:  64     62    14.00                 *     fldenv  (%eax)
-# CHECK-NEXT:  1      1      -                    *     fld1
+# CHECK-NEXT:  0      0      -                    *     fld1
 # CHECK-NEXT:  1      100   0.25                  *     fldl2e
 # CHECK-NEXT:  1      100   0.25                  *     fldl2t
 # CHECK-NEXT:  1      100   0.25                  *     fldlg2
 # CHECK-NEXT:  1      100   0.25                  *     fldln2
 # CHECK-NEXT:  1      100   0.25                  *     fldpi
-# CHECK-NEXT:  1      1      -                    *     fldz
+# CHECK-NEXT:  0      0      -                    *     fldz
 # CHECK-NEXT:  1      4     1.00                  *     fmul  %st(0), %st(1)
 # CHECK-NEXT:  1      4     1.00                  *     fmul  %st(2)
 # CHECK-NEXT:  2      11    1.00    *             *     fmuls (%ecx)
 # CHECK-NEXT:  2      11    1.00    *             *     fmull (%eax)
 # CHECK-NEXT:  1      4     1.00                  *     fmulp %st(1)
 # CHECK-NEXT:  1      4     1.00                  *     fmulp %st(2)
 # CHECK-NEXT:  3      14    1.00    *             *     fimuls  (%ecx)
 # CHECK-NEXT:  3      14    1.00    *             *     fimull  (%eax)

test/tools/llvm-mca/X86/SkylakeServer/resources-x86_64.s

 # CHECK-NEXT:  1      1     0.50                        btq $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btcq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btrq  $7, %rdi
 # CHECK-NEXT:  1      1     0.50                        btsq  $7, %rdi
 # CHECK-NEXT:  2      6     0.50    *                   btq $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btcq  $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btrq  $7, (%rax)
 # CHECK-NEXT:  4      6     1.00    *      *            btsq  $7, (%rax)
-# CHECK-NEXT:  1      1      -                    *     clc
+# CHECK-NEXT:  0      0      -                    *     clc
 # CHECK-NEXT:  1      1     0.25                        decb  %dil
 # CHECK-NEXT:  3      7     1.00    *      *            decb  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decw  %di
 # CHECK-NEXT:  3      7     1.00    *      *            decw  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decl  %edi
 # CHECK-NEXT:  3      7     1.00    *      *            decl  (%rax)
 # CHECK-NEXT:  1      1     0.25                        decq  %rdi
 # CHECK-NEXT:  3      7     1.00    *      *            decq  (%rax)

test/tools/llvm-mca/X86/SkylakeServer/resources-x87.s

 # CHECK-NEXT:  3      4     1.00           *      *     fisttpl (%ecx)
 # CHECK-NEXT:  3      4     1.00           *      *     fisttpll  (%eax)
 # CHECK-NEXT:  1      1     0.25                  *     fld %st(0)
 # CHECK-NEXT:  1      7     0.50    *             *     flds  (%edx)
 # CHECK-NEXT:  1      7     0.50    *             *     fldl  (%ecx)
 # CHECK-NEXT:  1      7     0.50    *             *     fldt  (%eax)
 # CHECK-NEXT:  3      7     1.00    *             *     fldcw (%eax)
 # CHECK-NEXT:  64     62    14.00                 *     fldenv  (%eax)
-# CHECK-NEXT:  1      1      -                    *     fld1
+# CHECK-NEXT:  0      0      -                    *     fld1
 # CHECK-NEXT:  1      100   0.25                  *     fldl2e
 # CHECK-NEXT:  1      100   0.25                  *     fldl2t
 # CHECK-NEXT:  1      100   0.25                  *     fldlg2
 # CHECK-NEXT:  1      100   0.25                  *     fldln2
 # CHECK-NEXT:  1      100   0.25                  *     fldpi
-# CHECK-NEXT:  1      1      -                    *     fldz
+# CHECK-NEXT:  0      0      -                    *     fldz
 # CHECK-NEXT:  1      4     1.00                  *     fmul  %st(0), %st(1)
 # CHECK-NEXT:  1      4     1.00                  *     fmul  %st(2)
 # CHECK-NEXT:  2      11    1.00    *             *     fmuls (%ecx)
 # CHECK-NEXT:  2      11    1.00    *             *     fmull (%eax)
 # CHECK-NEXT:  1      4     1.00                  *     fmulp %st(1)
 # CHECK-NEXT:  1      4     1.00                  *     fmulp %st(2)
 # CHECK-NEXT:  3      14    1.00    *             *     fimuls  (%ecx)
 # CHECK-NEXT:  3      14    1.00    *             *     fimull  (%eax)

utils/TableGen/GlobalISelEmitter.cpp

public:
   bool isHigherPriorityThan(const RuleMatcher &B) const;
 
   /// Report the maximum number of temporary operands needed by the rule
   /// matcher.
   unsigned countRendererFns() const;
 
   std::unique_ptr<PredicateMatcher> popFirstCondition() override;
   const PredicateMatcher &getFirstCondition() const override;
-  LLTCodeGen getFirstConditionAsRootType();
   bool hasFirstCondition() const override;
   unsigned getNumOperands() const;
   StringRef getOpcode() const;
 
   // FIXME: Remove this as soon as possible
   InstructionMatcher &insnmatchers_front() const { return *Matchers.front(); }
 
   unsigned allocateOutputInsnID() { return NextOutputInsnID++; }

 StringRef RuleMatcher::getOpcode() const {
   return Matchers.front()->getOpcode();
 }
 
 unsigned RuleMatcher::getNumOperands() const {
   return Matchers.front()->getNumOperands();
 }
 
-LLTCodeGen RuleMatcher::getFirstConditionAsRootType() {
-  InstructionMatcher &InsnMatcher = *Matchers.front();
-  if (!InsnMatcher.predicates_empty())
-    if (const auto *TM =
-            dyn_cast<LLTOperandMatcher>(&**InsnMatcher.predicates_begin()))
-      if (TM->getInsnVarID() == 0 && TM->getOpIdx() == 0)
-        return TM->getTy();
-  return {};
-}
-
 /// Generates code to check that the operand is a register defined by an
 /// instruction that matches the given instruction matcher.
 ///
 /// For example, the pattern:
 ///   (set $dst, (G_MUL (G_ADD $src1, $src2), $src3))
 /// would use an InstructionOperandMatcher for operand 1 of the G_MUL to match
 /// the:
 ///   (G_ADD $src1, $src2)