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[X86][Sched] Add InstRW for CLC on Intel after SNB.
ClosedPublic

Authored by courbet on May 25 2018, 1:50 AM.

Details

Summary

After SNB, Intel CPUs can rename CF independently of other EFLAGS,
so the renamer can zero it for free. Note that STC still consumes resources.

To reproduce: $ llvm-exegesis -mode=uops -opcode-name=CLC

On SNB:

---
key:
  opcode_name:     CLC
  mode:            uops
  config:          ''
cpu_name:        sandybridge
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
  - { key: '3', value: 0.0014, debug_string: SBPort0 }
  - { key: '4', value: 0.0013, debug_string: SBPort1 }
  - { key: '5', value: 0.0003, debug_string: SBPort4 }
  - { key: '6', value: 0.0029, debug_string: SBPort5 }
  - { key: '10', value: 0.0003, debug_string: SBPort23 }
error:           ''
info:            'instruction is serial, repeating a random one.
Snippet:
CLC
'
...

On HSW:

---
key:
  opcode_name:     CLC
  mode:            uops
  config:          ''
cpu_name:        haswell
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
  - { key: '3', value: 0.001, debug_string: HWPort0 }
  - { key: '4', value: 0.0009, debug_string: HWPort1 }
  - { key: '5', value: 0.0004, debug_string: HWPort2 }
  - { key: '6', value: 0.0006, debug_string: HWPort3 }
  - { key: '7', value: 0.0002, debug_string: HWPort4 }
  - { key: '8', value: 0.0012, debug_string: HWPort5 }
  - { key: '9', value: 0.0022, debug_string: HWPort6 }
  - { key: '10', value: 0.0001, debug_string: HWPort7 }
error:           ''
info:            'instruction is serial, repeating a random one.
Snippet:
CLC
'
...

Diff Detail

Repository
rL LLVM

Event Timeline

courbet created this revision.May 25 2018, 1:50 AM

Tests? Please can you add CLC to the relevant llvm-mca resource test files (or all of them if you wish - it's nice to keep those files the same for each CPU):

llvm\test\tools\llvm-mca\X86\SandyBridge\resources-x86_64.s
llvm\test\tools\llvm-mca\X86\Haswell\resources-x86_64.s
etc.

courbet updated this revision to Diff 148613.May 25 2018, 8:30 AM

Fix tests and add tests for llvm-mca

Thanks. Now I'll guess I'll go fix the WriteZero definition, that has one uop and latency 1 because that's the default :(

RKSimon accepted this revision.May 25 2018, 9:59 AM

LGTM - please commit this and then rebase D47377

This revision is now accepted and ready to land.May 25 2018, 9:59 AM
This revision was automatically updated to reflect the committed changes.