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Sparc.cpp

Differential D47137

[Sparc] Add floating-point register names
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Authored by dcederman on May 21 2018, 7:05 AM.

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jyknight

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rG8cc53aecad89: [Sparc] Add floating-point register names
rC333510: [Sparc] Add floating-point register names
rL333510: [Sparc] Add floating-point register names

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dcederman created this revision.May 21 2018, 7:05 AM

Herald added subscribers: cfe-commits, jrtc27, fedor.sergeev. · View Herald TranscriptMay 21 2018, 7:05 AM

Can you add a test that we support this? clang/test/CodeGen/sparcv8-inline-asm.c would be a good place to add a test case similar to that in clang/test/CodeGen/aarch64-inline-asm.c : test_gcc_registers.

What about the V9 dX and qX aliases and f32 to f63?

Added test cases, f32-f63, d0-d31, and q0-q15.

Herald added a subscriber: eraman. · View Herald TranscriptMay 23 2018, 7:07 AM

jyknight added inline comments.May 23 2018, 8:37 AM

lib/Basic/Targets/Sparc.cpp
31	There's no such register as f33 (nor any odd-numbered reg above f32).
45	AFAICT, gcc doesn't actually accept "d" and "q" aliases in its inline asm, so probably no point in LLVM doing so either.

jrtc27 added inline comments.May 23 2018, 9:35 AM

lib/Basic/Targets/Sparc.cpp
45	Ah you're right; trying to use it gives "invalid register name". Having said that, maybe it's a nice thing to support anyway?

Removed the non-existing registers f33, f35, and so on. I also removed the dX and qX aliases. After trying them they felt more confusing than helpful.

jyknight accepted this revision.May 29 2018, 11:45 AM

This revision is now accepted and ready to land.May 29 2018, 11:45 AM

Closed by commit rL333510: [Sparc] Add floating-point register names (authored by dcederman). · Explain WhyMay 29 2018, 11:06 PM

This revision was automatically updated to reflect the committed changes.

Herald added a subscriber: llvm-commits. · View Herald TranscriptMay 29 2018, 11:06 PM

Revision Contents

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lib/

Basic/

Targets/

Sparc.cpp

5 lines

Diff 147777

lib/Basic/Targets/Sparc.cpp

	Show All 16 Lines
	#include "llvm/ADT/StringSwitch.h"			#include "llvm/ADT/StringSwitch.h"

	using namespace clang;			using namespace clang;
	using namespace clang::targets;			using namespace clang::targets;

	const char *const SparcTargetInfo::GCCRegNames[] = {			const char *const SparcTargetInfo::GCCRegNames[] = {
	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",			"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
	"r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",			"r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
	"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"			"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
				"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10",
				"f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21",
				"f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
	};			};

	ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {			ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
				jyknightUnsubmitted Not Done Reply Inline Actions There's no such register as f33 (nor any odd-numbered reg above f32). jyknight: There's no such register as f33 (nor any odd-numbered reg above f32).
	return llvm::makeArrayRef(GCCRegNames);			return llvm::makeArrayRef(GCCRegNames);
	}			}

	const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {			const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
	{{"g0"}, "r0"}, {{"g1"}, "r1"}, {{"g2"}, "r2"}, {{"g3"}, "r3"},			{{"g0"}, "r0"}, {{"g1"}, "r1"}, {{"g2"}, "r2"}, {{"g3"}, "r3"},
	{{"g4"}, "r4"}, {{"g5"}, "r5"}, {{"g6"}, "r6"}, {{"g7"}, "r7"},			{{"g4"}, "r4"}, {{"g5"}, "r5"}, {{"g6"}, "r6"}, {{"g7"}, "r7"},
	{{"o0"}, "r8"}, {{"o1"}, "r9"}, {{"o2"}, "r10"}, {{"o3"}, "r11"},			{{"o0"}, "r8"}, {{"o1"}, "r9"}, {{"o2"}, "r10"}, {{"o3"}, "r11"},
	{{"o4"}, "r12"}, {{"o5"}, "r13"}, {{"o6", "sp"}, "r14"}, {{"o7"}, "r15"},			{{"o4"}, "r12"}, {{"o5"}, "r13"}, {{"o6", "sp"}, "r14"}, {{"o7"}, "r15"},
	{{"l0"}, "r16"}, {{"l1"}, "r17"}, {{"l2"}, "r18"}, {{"l3"}, "r19"},			{{"l0"}, "r16"}, {{"l1"}, "r17"}, {{"l2"}, "r18"}, {{"l3"}, "r19"},
	{{"l4"}, "r20"}, {{"l5"}, "r21"}, {{"l6"}, "r22"}, {{"l7"}, "r23"},			{{"l4"}, "r20"}, {{"l5"}, "r21"}, {{"l6"}, "r22"}, {{"l7"}, "r23"},
	{{"i0"}, "r24"}, {{"i1"}, "r25"}, {{"i2"}, "r26"}, {{"i3"}, "r27"},			{{"i0"}, "r24"}, {{"i1"}, "r25"}, {{"i2"}, "r26"}, {{"i3"}, "r27"},
	{{"i4"}, "r28"}, {{"i5"}, "r29"}, {{"i6", "fp"}, "r30"}, {{"i7"}, "r31"},			{{"i4"}, "r28"}, {{"i5"}, "r29"}, {{"i6", "fp"}, "r30"}, {{"i7"}, "r31"},
	};			};

				jyknightUnsubmitted Not Done Reply Inline Actions AFAICT, gcc doesn't actually accept "d" and "q" aliases in its inline asm, so probably no point in LLVM doing so either. jyknight: AFAICT, gcc doesn't actually accept "d" and "q" aliases in its inline asm, so probably no point…
				jrtc27Unsubmitted Not Done Reply Inline Actions Ah you're right; trying to use it gives "invalid register name". Having said that, maybe it's a nice thing to support anyway? jrtc27: Ah you're right; trying to use it gives "invalid register name". Having said that, maybe it's a…
	ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {			ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
	return llvm::makeArrayRef(GCCRegAliases);			return llvm::makeArrayRef(GCCRegAliases);
	}			}

	bool SparcTargetInfo::hasFeature(StringRef Feature) const {			bool SparcTargetInfo::hasFeature(StringRef Feature) const {
	return llvm::StringSwitch<bool>(Feature)			return llvm::StringSwitch<bool>(Feature)
	.Case("softfloat", SoftFloat)			.Case("softfloat", SoftFloat)
	.Case("sparc", true)			.Case("sparc", true)
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