[RISCV] Set CostPerUse for registers

[sabuasal]

Summary

Set CostPerUse higher for registers that are not used in the compressed
instruction set. This will influence the greedy register allocator to reduce
the use of registers that can't be encoded in 16 bit instructions. This
affects register allocation even when compressed instruction isn't targeted,
we see no major negative codegen impact.

[asb]

Thanks Sameer. With an explanatory comment in RISCVRegisterInfo.td this looks good to me.

When playing with this I left X0 with 0 CostPerUse despite the fact X0 isn't in GPRC, on the basis that discouraging the use of X0 seems like a poor strategy and is more likely to lead to undesirable codegen decisions when not optimising for codesize.

SP (X2) also has a CostPerUse=1 here. Although it's not in GPRC, there are of course specialised compressed instructions for stack load/store and addition meaning there's a good argument for leaving it with CostPerUse = 0. Given SP isn't allocatable anyway, there may be little/no impact either way.

lib/Target/RISCV/RISCVRegisterInfo.td

39 ↗

(On Diff #147410)

It would be worth adding a comment here to explain the motivation for setting CostPerUse and maybe saying that although it affects register allocation even when the compressed instruction set isn't targeted, we see no major negative codegen impact.

[sabuasal]

Added descriptive comments for rationale behind setting the CostPerUse property.

[sabuasal]

Ping?
is this good to merge?

[asb]

I tried leaving X2 with CostPerUse = 0 just to see if there were any cases where it could affect codegen. I wasn't able to generate any for the inputs I threw at it.

This looks good to me, but see my suggestion about tweaking the comment slightly.

lib/Target/RISCV/RISCVRegisterInfo.td

41 ↗

(On Diff #147591)

How about "CostPerUse is set higher for registers that may not be compressible as they are not part of GPRC, the most restrictive register class used by the compressed instruction set." A number of compressed instructions of course can access a wider range of registers, so this is a pessimistic choice.

[sabuasal]

Updated the comment.

I also experimented with leaving the X2 out, I didn't see any changes.

llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.td

class RISCVReg64<RISCVReg32 subreg> : Register<""> {
   let AsmName = subreg.AsmName;
   let AltNames = subreg.AltNames;
 }
 
 def ABIRegAltName : RegAltNameIndex;
 } // Namespace = "RISCV"
 
 // Integer registers
+// CostPerUse is set higher for registers that may not be compressible as they
+// are not part of GPRC, the most restrictive register class used by the
+// compressed instruction set. This will influence the greedy register
+// allocator to reduce the use of registers that can't be encoded in 16 bit
+// instructions. This affects register allocation even when compressed
+// instruction isn't targeted, we see no major negative codegen impact.
+
 let RegAltNameIndices = [ABIRegAltName] in {
   def X0  : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
+  let CostPerUse = 1 in {
   def X1  : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
   def X2  : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
   def X3  : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
   def X4  : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
   def X5  : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
   def X6  : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
   def X7  : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
+  }
   def X8  : RISCVReg<8, "x8", ["s0"]>, DwarfRegNum<[8]>;
   def X9  : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>;
   def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>;
   def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>;
   def X12 : RISCVReg<12,"x12", ["a2"]>, DwarfRegNum<[12]>;
   def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>;
   def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>;
   def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>;
+  let CostPerUse = 1 in {
   def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>;
   def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>;
   def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>;
   def X19 : RISCVReg<19,"x19", ["s3"]>, DwarfRegNum<[19]>;
   def X20 : RISCVReg<20,"x20", ["s4"]>, DwarfRegNum<[20]>;
   def X21 : RISCVReg<21,"x21", ["s5"]>, DwarfRegNum<[21]>;
   def X22 : RISCVReg<22,"x22", ["s6"]>, DwarfRegNum<[22]>;
   def X23 : RISCVReg<23,"x23", ["s7"]>, DwarfRegNum<[23]>;
   def X24 : RISCVReg<24,"x24", ["s8"]>, DwarfRegNum<[24]>;
   def X25 : RISCVReg<25,"x25", ["s9"]>, DwarfRegNum<[25]>;
   def X26 : RISCVReg<26,"x26", ["s10"]>, DwarfRegNum<[26]>;
   def X27 : RISCVReg<27,"x27", ["s11"]>, DwarfRegNum<[27]>;
   def X28 : RISCVReg<28,"x28", ["t3"]>, DwarfRegNum<[28]>;
   def X29 : RISCVReg<29,"x29", ["t4"]>, DwarfRegNum<[29]>;
   def X30 : RISCVReg<30,"x30", ["t5"]>, DwarfRegNum<[30]>;
   def X31 : RISCVReg<31,"x31", ["t6"]>, DwarfRegNum<[31]>;
   }
+}
 
 def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode],
                                [i32,  i64,  i32]>;
 
 // The order of registers represents the preferred allocation sequence.
 // Registers are listed in the order caller-save, callee-save, specials.
 def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add
     (sequence "X%u", 10, 17),

llvm/trunk/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll

 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    sw s6, 4(sp)
 ; RV32I-NEXT:    sw s7, 0(sp)
-; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s3, a1
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    not a1, s3
+; RV32I-NEXT:    not a1, s4
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    lui a1, 349525
 ; RV32I-NEXT:    addi s5, a1, 1365
 ; RV32I-NEXT:    srli a1, a0, 1
 ; RV32I-NEXT:    and a1, a1, s5
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    lui a1, 209715
-; RV32I-NEXT:    addi s6, a1, 819
-; RV32I-NEXT:    and a1, a0, s6
+; RV32I-NEXT:    addi s1, a1, 819
+; RV32I-NEXT:    and a1, a0, s1
 ; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    and a0, a0, s6
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    lui a1, 4112
-; RV32I-NEXT:    addi s4, a1, 257
+; RV32I-NEXT:    addi s6, a1, 257
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi s7, a1, -241
 ; RV32I-NEXT:    and a0, a0, s7
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a1, s6
 ; RV32I-NEXT:    call __mulsi3
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    addi a0, s2, -1
-; RV32I-NEXT:    not a1, s2
+; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    addi a0, s3, -1
+; RV32I-NEXT:    not a1, s3
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 1
 ; RV32I-NEXT:    and a1, a1, s5
 ; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    and a1, a0, s6
+; RV32I-NEXT:    and a1, a0, s1
 ; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    and a0, a0, s6
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    and a0, a0, s7
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a1, s6
 ; RV32I-NEXT:    call __mulsi3
-; RV32I-NEXT:    bnez s3, .LBB7_2
+; RV32I-NEXT:    bnez s4, .LBB7_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    addi a0, a0, 32
 ; RV32I-NEXT:    j .LBB7_3
 ; RV32I-NEXT:  .LBB7_2:
-; RV32I-NEXT:    srli a0, s1, 24
+; RV32I-NEXT:    srli a0, s2, 24
 ; RV32I-NEXT:  .LBB7_3:
 ; RV32I-NEXT:    mv a1, zero
 ; RV32I-NEXT:    lw s7, 0(sp)
 ; RV32I-NEXT:    lw s6, 4(sp)
 ; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)

 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    sw s5, 8(sp)
 ; RV32I-NEXT:    sw s6, 4(sp)
 ; RV32I-NEXT:    sw s7, 0(sp)
-; RV32I-NEXT:    mv s2, a1
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s3, a1
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    not a1, s3
+; RV32I-NEXT:    not a1, s4
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    lui a1, 349525
 ; RV32I-NEXT:    addi s5, a1, 1365
 ; RV32I-NEXT:    srli a1, a0, 1
 ; RV32I-NEXT:    and a1, a1, s5
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    lui a1, 209715
-; RV32I-NEXT:    addi s6, a1, 819
-; RV32I-NEXT:    and a1, a0, s6
+; RV32I-NEXT:    addi s1, a1, 819
+; RV32I-NEXT:    and a1, a0, s1
 ; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    and a0, a0, s6
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    lui a1, 4112
-; RV32I-NEXT:    addi s4, a1, 257
+; RV32I-NEXT:    addi s6, a1, 257
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi s7, a1, -241
 ; RV32I-NEXT:    and a0, a0, s7
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a1, s6
 ; RV32I-NEXT:    call __mulsi3
-; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    addi a0, s2, -1
-; RV32I-NEXT:    not a1, s2
+; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    addi a0, s3, -1
+; RV32I-NEXT:    not a1, s3
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 1
 ; RV32I-NEXT:    and a1, a1, s5
 ; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    and a1, a0, s6
+; RV32I-NEXT:    and a1, a0, s1
 ; RV32I-NEXT:    srli a0, a0, 2
-; RV32I-NEXT:    and a0, a0, s6
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    and a0, a0, s7
-; RV32I-NEXT:    mv a1, s4
+; RV32I-NEXT:    mv a1, s6
 ; RV32I-NEXT:    call __mulsi3
-; RV32I-NEXT:    bnez s3, .LBB11_2
+; RV32I-NEXT:    bnez s4, .LBB11_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    addi a0, a0, 32
 ; RV32I-NEXT:    j .LBB11_3
 ; RV32I-NEXT:  .LBB11_2:
-; RV32I-NEXT:    srli a0, s1, 24
+; RV32I-NEXT:    srli a0, s2, 24
 ; RV32I-NEXT:  .LBB11_3:
 ; RV32I-NEXT:    mv a1, zero
 ; RV32I-NEXT:    lw s7, 0(sp)
 ; RV32I-NEXT:    lw s6, 4(sp)
 ; RV32I-NEXT:    lw s5, 8(sp)
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)

llvm/trunk/test/CodeGen/RISCV/calling-conv.ll

 ; RV32I-FPELIM-LABEL: callee_scalars:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -32
 ; RV32I-FPELIM-NEXT:    sw ra, 28(sp)
 ; RV32I-FPELIM-NEXT:    sw s1, 24(sp)
 ; RV32I-FPELIM-NEXT:    sw s2, 20(sp)
 ; RV32I-FPELIM-NEXT:    sw s3, 16(sp)
 ; RV32I-FPELIM-NEXT:    sw s4, 12(sp)
-; RV32I-FPELIM-NEXT:    mv s1, a4
-; RV32I-FPELIM-NEXT:    mv s2, a3
-; RV32I-FPELIM-NEXT:    mv s3, a1
-; RV32I-FPELIM-NEXT:    mv s4, a0
+; RV32I-FPELIM-NEXT:    mv s2, a4
+; RV32I-FPELIM-NEXT:    mv s3, a3
+; RV32I-FPELIM-NEXT:    mv s4, a1
+; RV32I-FPELIM-NEXT:    mv s1, a0
 ; RV32I-FPELIM-NEXT:    mv a0, a5
 ; RV32I-FPELIM-NEXT:    mv a1, a6
 ; RV32I-FPELIM-NEXT:    call __fixdfsi
-; RV32I-FPELIM-NEXT:    add a1, s4, s3
+; RV32I-FPELIM-NEXT:    add a1, s1, s4
+; RV32I-FPELIM-NEXT:    add a1, a1, s3
 ; RV32I-FPELIM-NEXT:    add a1, a1, s2
-; RV32I-FPELIM-NEXT:    add a1, a1, s1
 ; RV32I-FPELIM-NEXT:    add a0, a1, a0
 ; RV32I-FPELIM-NEXT:    lw s4, 12(sp)
 ; RV32I-FPELIM-NEXT:    lw s3, 16(sp)
 ; RV32I-FPELIM-NEXT:    lw s2, 20(sp)
 ; RV32I-FPELIM-NEXT:    lw s1, 24(sp)
 ; RV32I-FPELIM-NEXT:    lw ra, 28(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 32
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: callee_scalars:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -32
 ; RV32I-WITHFP-NEXT:    sw ra, 28(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 24(sp)
 ; RV32I-WITHFP-NEXT:    sw s1, 20(sp)
 ; RV32I-WITHFP-NEXT:    sw s2, 16(sp)
 ; RV32I-WITHFP-NEXT:    sw s3, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s4, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 32
-; RV32I-WITHFP-NEXT:    mv s1, a4
-; RV32I-WITHFP-NEXT:    mv s2, a3
-; RV32I-WITHFP-NEXT:    mv s3, a1
-; RV32I-WITHFP-NEXT:    mv s4, a0
+; RV32I-WITHFP-NEXT:    mv s2, a4
+; RV32I-WITHFP-NEXT:    mv s3, a3
+; RV32I-WITHFP-NEXT:    mv s4, a1
+; RV32I-WITHFP-NEXT:    mv s1, a0
 ; RV32I-WITHFP-NEXT:    mv a0, a5
 ; RV32I-WITHFP-NEXT:    mv a1, a6
 ; RV32I-WITHFP-NEXT:    call __fixdfsi
-; RV32I-WITHFP-NEXT:    add a1, s4, s3
+; RV32I-WITHFP-NEXT:    add a1, s1, s4
+; RV32I-WITHFP-NEXT:    add a1, a1, s3
 ; RV32I-WITHFP-NEXT:    add a1, a1, s2
-; RV32I-WITHFP-NEXT:    add a1, a1, s1
 ; RV32I-WITHFP-NEXT:    add a0, a1, a0
 ; RV32I-WITHFP-NEXT:    lw s4, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw s3, 12(sp)
 ; RV32I-WITHFP-NEXT:    lw s2, 16(sp)
 ; RV32I-WITHFP-NEXT:    lw s1, 20(sp)
 ; RV32I-WITHFP-NEXT:    lw s0, 24(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 28(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 32

llvm/trunk/test/CodeGen/RISCV/double-mem.ll

 
 define double @fld_stack(double %a) nounwind {
 ; RV32IFD-LABEL: fld_stack:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -32
 ; RV32IFD-NEXT:    sw ra, 28(sp)
 ; RV32IFD-NEXT:    sw s1, 24(sp)
 ; RV32IFD-NEXT:    sw s2, 20(sp)
-; RV32IFD-NEXT:    mv s1, a1
-; RV32IFD-NEXT:    mv s2, a0
+; RV32IFD-NEXT:    mv s2, a1
+; RV32IFD-NEXT:    mv s1, a0
 ; RV32IFD-NEXT:    addi a0, sp, 8
 ; RV32IFD-NEXT:    call notdead
-; RV32IFD-NEXT:    sw s2, 0(sp)
-; RV32IFD-NEXT:    sw s1, 4(sp)
+; RV32IFD-NEXT:    sw s1, 0(sp)
+; RV32IFD-NEXT:    sw s2, 4(sp)
 ; RV32IFD-NEXT:    fld ft0, 0(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
 ; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
 ; RV32IFD-NEXT:    fsd ft0, 0(sp)
 ; RV32IFD-NEXT:    lw a0, 0(sp)
 ; RV32IFD-NEXT:    lw a1, 4(sp)
 ; RV32IFD-NEXT:    lw s2, 20(sp)
 ; RV32IFD-NEXT:    lw s1, 24(sp)

llvm/trunk/test/CodeGen/RISCV/remat.ll

 ; RV32I-NEXT:    lw a0, %lo(a)(s3)
 ; RV32I-NEXT:    beqz a0, .LBB0_11
 ; RV32I-NEXT:  # %bb.1: # %for.body.preheader
 ; RV32I-NEXT:    lui s5, %hi(k)
 ; RV32I-NEXT:    lui s6, %hi(j)
 ; RV32I-NEXT:    lui s7, %hi(i)
 ; RV32I-NEXT:    lui s9, %hi(g)
 ; RV32I-NEXT:    lui s10, %hi(f)
-; RV32I-NEXT:    lui s11, %hi(e)
+; RV32I-NEXT:    lui s1, %hi(e)
 ; RV32I-NEXT:    lui s8, %hi(d)
-; RV32I-NEXT:    addi s1, zero, 32
+; RV32I-NEXT:    addi s11, zero, 32
 ; RV32I-NEXT:    lui s2, %hi(c)
 ; RV32I-NEXT:    lui s4, %hi(b)
 ; RV32I-NEXT:  .LBB0_2: # %for.body
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    lui a1, %hi(l)
 ; RV32I-NEXT:    lw a1, %lo(l)(a1)
 ; RV32I-NEXT:    beqz a1, .LBB0_4
 ; RV32I-NEXT:  # %bb.3: # %if.then
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
-; RV32I-NEXT:    lw a4, %lo(e)(s11)
+; RV32I-NEXT:    lw a4, %lo(e)(s1)
 ; RV32I-NEXT:    lw a3, %lo(d)(s8)
 ; RV32I-NEXT:    lw a2, %lo(c)(s2)
 ; RV32I-NEXT:    lw a1, %lo(b)(s4)
-; RV32I-NEXT:    mv a5, s1
+; RV32I-NEXT:    mv a5, s11
 ; RV32I-NEXT:    call foo
 ; RV32I-NEXT:  .LBB0_4: # %if.end
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
 ; RV32I-NEXT:    lw a0, %lo(k)(s5)
 ; RV32I-NEXT:    beqz a0, .LBB0_6
 ; RV32I-NEXT:  # %bb.5: # %if.then3
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
 ; RV32I-NEXT:    lw a4, %lo(f)(s10)
-; RV32I-NEXT:    lw a3, %lo(e)(s11)
+; RV32I-NEXT:    lw a3, %lo(e)(s1)
 ; RV32I-NEXT:    lw a2, %lo(d)(s8)
 ; RV32I-NEXT:    lw a1, %lo(c)(s2)
 ; RV32I-NEXT:    lw a0, %lo(b)(s4)
 ; RV32I-NEXT:    addi a5, zero, 64
 ; RV32I-NEXT:    call foo
 ; RV32I-NEXT:  .LBB0_6: # %if.end5
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
 ; RV32I-NEXT:    lw a0, %lo(j)(s6)
 ; RV32I-NEXT:    beqz a0, .LBB0_8
 ; RV32I-NEXT:  # %bb.7: # %if.then7
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
 ; RV32I-NEXT:    lw a4, %lo(g)(s9)
 ; RV32I-NEXT:    lw a3, %lo(f)(s10)
-; RV32I-NEXT:    lw a2, %lo(e)(s11)
+; RV32I-NEXT:    lw a2, %lo(e)(s1)
 ; RV32I-NEXT:    lw a1, %lo(d)(s8)
 ; RV32I-NEXT:    lw a0, %lo(c)(s2)
-; RV32I-NEXT:    mv a5, s1
+; RV32I-NEXT:    mv a5, s11
 ; RV32I-NEXT:    call foo
 ; RV32I-NEXT:  .LBB0_8: # %if.end9
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
 ; RV32I-NEXT:    lw a0, %lo(i)(s7)
 ; RV32I-NEXT:    beqz a0, .LBB0_10
 ; RV32I-NEXT:  # %bb.9: # %if.then11
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
 ; RV32I-NEXT:    lui a0, %hi(h)
 ; RV32I-NEXT:    lw a4, %lo(h)(a0)
 ; RV32I-NEXT:    lw a3, %lo(g)(s9)
 ; RV32I-NEXT:    lw a2, %lo(f)(s10)
-; RV32I-NEXT:    lw a1, %lo(e)(s11)
+; RV32I-NEXT:    lw a1, %lo(e)(s1)
 ; RV32I-NEXT:    lw a0, %lo(d)(s8)
-; RV32I-NEXT:    mv a5, s1
+; RV32I-NEXT:    mv a5, s11
 ; RV32I-NEXT:    call foo
 ; RV32I-NEXT:  .LBB0_10: # %for.inc
 ; RV32I-NEXT:    # in Loop: Header=BB0_2 Depth=1
 ; RV32I-NEXT:    lw a0, %lo(a)(s3)
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    sw a0, %lo(a)(s3)
 ; RV32I-NEXT:    bnez a0, .LBB0_2
 ; RV32I-NEXT:  .LBB0_11: # %for.end