[mips] Correct the predicates of arithmetic and logic instructions.

[sdardis]

Summary

As part of this effort, duplicate and correct the predicates of some
aliases. Also disable code generation of some short form instructions
for FastISel, as it would otherwise reject them.

[atanasyan]

LGTM

[sdardis]

Abandoning this, I realised that D47075 is more or less the same patch with the additional changes for microMIPS32R6. I must have gotten confused when preparing these patches for review.

lib/Target/Mips/MicroMipsInstrInfo.td

 
 class MtCop0MM<string opstr, RegisterOperand DstRC,
                RegisterOperand SrcRC, InstrItinClass Itin> :
   InstSE<(outs DstRC:$rs), (ins SrcRC:$rt, uimm3:$sel),
           !strconcat(opstr, "\t$rt, $rs, $sel"), [], Itin, FrmR> {
   let BaseOpcode = opstr;
 }
 
+let FastISelShouldIgnore = 1 in {
   def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
       ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
   def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
       LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6;
+}
+
 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
                 ISA_MICROMIPS_NOT_32R6;
 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
                ISA_MICROMIPS_NOT_32R6;
+let FastISelShouldIgnore = 1 in
   def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
                 ISA_MICROMIPS_NOT_32R6;
 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
     SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
     SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
 
+let FastISelShouldIgnore = 1 in {
   def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
                   ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
   def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
                  LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6;
+}
 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
                         mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
                         mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
                       LOAD_STORE_FM_MM16<0x1a>;
 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
                         II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;

 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips, NotMips32r6,
                                                   NotMips64r6] in {
   /// Compact Branch Instructions
   def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
                  COMPACT_BRANCH_FM_MM<0x7>;
   def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
                  COMPACT_BRANCH_FM_MM<0x5>;
 }
-let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
+let DecoderNamespace = "MicroMips" in {
   /// Arithmetic Instructions (ALU Immediate)
   def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU>,
-                 ADDI_FM_MM<0xc>;
+                 ADDI_FM_MM<0xc>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def ADDi_MM  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd, II_ADDI>,
-                 ADDI_FM_MM<0x4>;
+                 ADDI_FM_MM<0x4>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def SLTi_MM  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
-                 SLTI_FM_MM<0x24>;
+                 SLTI_FM_MM<0x24>, ISA_MICROMIPS;
   def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
-                 SLTI_FM_MM<0x2c>;
+                 SLTI_FM_MM<0x2c>, ISA_MICROMIPS;
   def ANDi_MM  : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>,
-                 ADDI_FM_MM<0x34>;
+                 ADDI_FM_MM<0x34>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def ORi_MM   : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
-                                    or>, ADDI_FM_MM<0x14>;
+                                    or>, ADDI_FM_MM<0x14>,
+                 ISA_MICROMIPS32_NOT_MIPS32R6;
   def XORi_MM  : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
-                                    immZExt16, xor>, ADDI_FM_MM<0x1c>;
-  def LUi_MM   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM_MM;
+                                    immZExt16, xor>, ADDI_FM_MM<0x1c>,
+                 ISA_MICROMIPS32_NOT_MIPS32R6;
+  def LUi_MM   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM_MM,
+                 ISA_MICROMIPS32_NOT_MIPS32R6;
 
   def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
                      LW_FM_MM<0xc>;
 
   /// Arithmetic Instructions (3-Operand, R-Type)
   def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
-                 ADD_FM_MM<0, 0x150>;
+                 ADD_FM_MM<0, 0x150>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def SUBu_MM  : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
-                 ADD_FM_MM<0, 0x1d0>;
+                 ADD_FM_MM<0, 0x1d0>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def MUL_MM   : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL>,
-                 ADD_FM_MM<0, 0x210>;
+                 ADD_FM_MM<0, 0x210>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def ADD_MM   : MMRel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>,
-                 ADD_FM_MM<0, 0x110>;
+                 ADD_FM_MM<0, 0x110>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def SUB_MM   : MMRel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>,
-                 ADD_FM_MM<0, 0x190>;
-  def SLT_MM   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
+                 ADD_FM_MM<0, 0x190>, ISA_MICROMIPS32_NOT_MIPS32R6;
+  def SLT_MM   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>,
+                 ISA_MICROMIPS;
   def SLTu_MM  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
-                 ADD_FM_MM<0, 0x390>;
+                 ADD_FM_MM<0, 0x390>, ISA_MICROMIPS;
   def AND_MM   : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
-                 ADD_FM_MM<0, 0x250>;
+                 ADD_FM_MM<0, 0x250>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def OR_MM    : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
-                 ADD_FM_MM<0, 0x290>;
+                 ADD_FM_MM<0, 0x290>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def XOR_MM   : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
-                 ADD_FM_MM<0, 0x310>;
+                 ADD_FM_MM<0, 0x310>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def NOR_MM   : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
   def MULT_MM  : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
-                 MULT_FM_MM<0x22c>;
+                 MULT_FM_MM<0x22c>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
-                 MULT_FM_MM<0x26c>;
+                 MULT_FM_MM<0x26c>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def SDIV_MM  : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
-                 MULT_FM_MM<0x2ac>, ISA_MIPS1_NOT_32R6_64R6;
+                 MULT_FM_MM<0x2ac>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def UDIV_MM  : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
-                 MULT_FM_MM<0x2ec>, ISA_MIPS1_NOT_32R6_64R6;
+                 MULT_FM_MM<0x2ec>, ISA_MICROMIPS32_NOT_MIPS32R6;
 
   /// Arithmetic Instructions with PC and Immediate
   def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
 
   /// Shift Instructions
   def SLL_MM   : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
                  SRA_FM_MM<0, 0>, ISA_MICROMIPS;
   def SRL_MM   : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
                  SRA_FM_MM<0x40, 0>, ISA_MICROMIPS;
   def SRA_MM   : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
                  SRA_FM_MM<0x80, 0>, ISA_MICROMIPS;
   def SLLV_MM  : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
                  SRLV_FM_MM<0x10, 0>, ISA_MICROMIPS;
   def SRLV_MM  : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
                  SRLV_FM_MM<0x50, 0>, ISA_MICROMIPS;
   def SRAV_MM  : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
                  SRLV_FM_MM<0x90, 0>, ISA_MICROMIPS;
   def ROTR_MM  : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
-                 SRA_FM_MM<0xc0, 0> {
+                 SRA_FM_MM<0xc0, 0>, ISA_MICROMIPS {
     list<dag> Pattern = [(set GPR32Opnd:$rd,
                           (rotr GPR32Opnd:$rt, immZExt5:$shamt))];
   }
   def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
-                 SRLV_FM_MM<0xd0, 0> {
+                 SRLV_FM_MM<0xd0, 0>, ISA_MICROMIPS {
     list<dag> Pattern = [(set GPR32Opnd:$rd,
                           (rotr GPR32Opnd:$rt, GPR32Opnd:$rs))];
   }
 
   /// Load and Store Instructions - aligned
   let DecoderMethod = "DecodeMemMMImm16" in {
     def LB_MM  : LoadMemory<"lb", GPR32Opnd, mem_mm_16, sextloadi8, II_LB>,
                  MMRel, LW_FM_MM<0x7>, ISA_MICROMIPS;
let Predicates = [InMicroMips] in {
   def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
                                      II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
 
   def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>, ISA_MICROMIPS;
   def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
   def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
   def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MICROMIPS;
   def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MICROMIPS;
+  def : MipsInstAlias<"neg $rt, $rs",
+                      (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
+        ISA_MICROMIPS;
+  def : MipsInstAlias<"neg $rt",
+                      (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
+        ISA_MICROMIPS;
+  def : MipsInstAlias<"negu $rt, $rs",
+                      (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
+        ISA_MICROMIPS;
+  def : MipsInstAlias<"negu $rt",
+                      (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
+        ISA_MICROMIPS;
   def : MipsInstAlias<"teq $rs, $rt",
                       (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
   def : MipsInstAlias<"tge $rs, $rt",
                       (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
   def : MipsInstAlias<"tgeu $rs, $rt",
                       (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
   def : MipsInstAlias<"tlt $rs, $rt",
                       (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;

lib/Target/Mips/MipsInstrInfo.td

def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
       ISA_MIPS1_NOT_32R6_64R6;
 
 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
 let Predicates = [NotInMicroMips] in {
 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
 }
 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>,
       ISA_MIPS32;
+let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsInstAlias<"neg $rt, $rs",
                       (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
   def : MipsInstAlias<"neg $rt",
                       (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>;
   def : MipsInstAlias<"negu $rt, $rs",
                       (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
   def : MipsInstAlias<"negu $rt",
                       (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>;
-let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsInstAlias<
           "sgt $rd, $rs, $rt",
           (SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
   def : MipsInstAlias<
           "sgt $rs, $rt",
           (SLT GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
   def : MipsInstAlias<
           "sgtu $rd, $rs, $rt",

test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

 0x26 0x31 0x67 0xc5 # CHECK: addiu $9, $6, -15001
 0x26 0x11 0x67 0x45 # CHECK: addi $9, $6, 17767
 0x26 0x31 0x67 0xc5 # CHECK: addiu $9, $6, -15001
 0xe6 0x00 0x50 0x49 # CHECK: addu $9, $6, $7
 0x80 0x43 0xe6 0xff # CHECK: bc1f -48
 0xa0 0x43 0xe2 0xff # CHECK: bc1t -56
 0xe6 0x00 0x90 0x49 # CHECK: sub $9, $6, $7
 0xa3 0x00 0xd0 0x21 # CHECK: subu  $4, $3, $5
-0xe0 0x00 0x90 0x31 # CHECK: sub $6, $zero, $7
-0xe0 0x00 0xd0 0x31 # CHECK: subu $6, $zero, $7
+0xe0 0x00 0x90 0x31 # CHECK: neg $6, $7
+0xe0 0x00 0xd0 0x31 # CHECK: negu $6, $7
 0x08 0x00 0x50 0x39 # CHECK: addu $7, $8, $zero
 0xa3 0x00 0x50 0x1b # CHECK: slt $3, $3, $5
 0x63 0x90 0x67 0x00 # CHECK: slti $3, $3, 103
 0x63 0x90 0x67 0x00 # CHECK: slti $3, $3, 103
 0x63 0xb0 0x67 0x00 # CHECK: sltiu $3, $3, 103
 0xa3 0x00 0x90 0x1b # CHECK: sltu $3, $3, $5
 0xa9 0x41 0x67 0x45 # CHECK: lui $9, 17767
 0xe6 0x00 0x50 0x4a # CHECK: and $9, $6, $7

test/MC/Disassembler/Mips/micromips32r3/valid.txt

 0x31 0x26 0xc5 0x67 # CHECK: addiu $9, $6, -15001
 0x11 0x26 0x45 0x67 # CHECK: addi $9, $6, 17767
 0x31 0x26 0xc5 0x67 # CHECK: addiu $9, $6, -15001
 0x00 0xe6 0x49 0x50 # CHECK: addu $9, $6, $7
 0x43 0x80 0xff 0xe6 # CHECK: bc1f -48
 0x43 0xa0 0xff 0xe2 # CHECK: bc1t -56
 0x00 0xe6 0x49 0x90 # CHECK: sub $9, $6, $7
 0x00 0xa3 0x21 0xd0 # CHECK: subu $4, $3, $5
-0x00 0xe0 0x31 0x90 # CHECK: sub $6, $zero, $7
-0x00 0xe0 0x31 0xd0 # CHECK: subu $6, $zero, $7
+0x00 0xe0 0x31 0x90 # CHECK: neg $6, $7
+0x00 0xe0 0x31 0xd0 # CHECK: negu $6, $7
 0x00 0x08 0x39 0x50 # CHECK: addu $7, $8, $zero
 0x00 0xa3 0x1b 0x50 # CHECK: slt $3, $3, $5
 0x90 0x63 0x00 0x67 # CHECK: slti $3, $3, 103
 0x90 0x63 0x00 0x67 # CHECK: slti $3, $3, 103
 0xb0 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
 0x00 0xa3 0x1b 0x90 # CHECK: sltu $3, $3, $5
 0x41 0xa9 0x45 0x67 # CHECK: lui $9, 17767
 0x00 0xe6 0x4a 0x50 # CHECK: and $9, $6, $7

test/MC/Mips/micromips/valid.s

 addi $9, $6, 17767          # CHECK: addi $9, $6, 17767     # encoding: [0x11,0x26,0x45,0x67]
 addiu $9, $6, -15001        # CHECK: addiu $9, $6, -15001   # encoding: [0x31,0x26,0xc5,0x67]
 addu $9, $6, $7             # CHECK: addu $9, $6, $7        # encoding: [0x00,0xe6,0x49,0x50]
 sub $9, $6, $7              # CHECK: sub $9, $6, $7         # encoding: [0x00,0xe6,0x49,0x90]
 subu $4, $3, $5             # CHECK: subu $4, $3, $5        # encoding: [0x00,0xa3,0x21,0xd0]
 sub $6, $zero, $7           # CHECK: neg $6, $7             # encoding: [0x00,0xe0,0x31,0x90]
 sub.d $f0, $f2, $f4         # CHECK: sub.d $f0, $f2, $f4    # encoding: [0x54,0x82,0x01,0x70]
                             # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} FSUB_D32_MM
-subu $6, $zero, $7          # CHECK: subu $6, $zero, $7     # encoding: [0x00,0xe0,0x31,0xd0]
+subu $6, $zero, $7          # CHECK: negu $6, $7            # encoding: [0x00,0xe0,0x31,0xd0]
 addu $7, $8, $zero          # CHECK: addu $7, $8, $zero     # encoding: [0x00,0x08,0x39,0x50]
 slt $3, $3, $5              # CHECK: slt $3, $3, $5         # encoding: [0x00,0xa3,0x1b,0x50]
 slti $3, $3, 103            # CHECK: slti $3, $3, 103       # encoding: [0x90,0x63,0x00,0x67]
 slti $3, $3, 103            # CHECK: slti $3, $3, 103       # encoding: [0x90,0x63,0x00,0x67]
 sltiu $3, $3, 103           # CHECK: sltiu $3, $3, 103      # encoding: [0xb0,0x63,0x00,0x67]
 sltu $3, $3, $5             # CHECK: sltu $3, $3, $5        # encoding: [0x00,0xa3,0x1b,0x90]
 lui $9, 17767               # CHECK: lui $9, 17767          # encoding: [0x41,0xa9,0x45,0x67]
 and $9, $6, $7              # CHECK: and $9, $6, $7         # encoding: [0x00,0xe6,0x4a,0x50]