[FastISel] Permit instructions to be skipped for FastISel generation.

[sdardis]

Summary

Some ISA's such as microMIPS32(R6) have instructions which are near identical
for code generation purposes, e.g. xor and xor16. These instructions take the
same value types for operands and return values, have the same
instruction predicates and map to the same ISD opcode. (These instructions do
differ by register classes.)

In such cases, the FastISel generator rejects the instruction definition.

This patch borrows the 'FastIselShouldIgnore' bit from rL129692 and enables
applying it to an instruction definition.

[mcrosier]

Can you please add a test case?

Is the intent here just to bail early in order to save compile time?

[sdardis]

Include test case.

[sdardis]

Is the intent here just to bail early in order to save compile time?

The intent here is to deal with instructions like addu16 in microMIPS by excluding them from consideration for FastISel altogether as currently they can't be handled:

cd /Users/sdardis/dev/llvm/llvmbuild3 && /Users/sdardis/dev/llvm/llvmbuild3/bin/llvm-tblgen -gen-fast-isel -I /Users/sdardis/dev/llvm/llvm/lib/Target/Mips -I /Users/sdardis/dev/llvm/llvm/include -I /Users/sdardis/dev/llvm/llvm/lib/Target /Users/sdardis/dev/llvm/llvm/lib/Target/Mips/Mips.td -o lib/Target/Mips/MipsGenFastISel.inc.tmp -d lib/Target/Mips/MipsGenFastISel.inc.d
Included from /Users/sdardis/dev/llvm/llvm/lib/Target/Mips/Mips.td:60:
Included from /Users/sdardis/dev/llvm/llvm/lib/Target/Mips/MipsInstrInfo.td:3185:
/Users/sdardis/dev/llvm/llvm/lib/Target/Mips/MicroMipsInstrInfo.td:747:3: error: Duplicate predicate in FastISel table!

This error occurs wile building LLVM with the D46956 applied and a similar error for the attached test case. This patch allows FastISel generation to succeed.

[mcrosier]

Okay, now I understand. Seems like a reasonable extension.

Can you point me at the change that actually uses this new functionality?

utils/TableGen/FastISelEmitter.cpp

452 ↗

(On Diff #147450)

Please don't add white space.

[sdardis]

The two dependant patches (https://reviews.llvm.org/D46956 and https://reviews.llvm.org/D47075) make use of this functionality. I can't commit them yet without this patch, as they'll break the build for any builder which compiles the MIPS backend.

utils/TableGen/FastISelEmitter.cpp

452 ↗

(On Diff #147450)

Will fix this.

[mcrosier]

LGTM.

llvm/trunk/include/llvm/Target/Target.td

class Instruction {
   string AsmVariantName = "";
 
   ///@}
 
   /// UseNamedOperandTable - If set, the operand indices of this instruction
   /// can be queried via the getNamedOperandIdx() function which is generated
   /// by TableGen.
   bit UseNamedOperandTable = 0;
+
+  /// Should FastISel ignore this instruction. For certain ISAs, they have
+  /// instructions which map to the same ISD Opcode, value type operands and
+  /// instruction selection predicates. FastISel cannot handle such cases, but
+  /// SelectionDAG can.
+  bit FastISelShouldIgnore = 0;
 }
 
 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
 /// Which instruction it expands to and how the operands map from the
 /// pseudo.
 class PseudoInstExpansion<dag Result> {
   dag ResultInst = Result;     // The instruction to generate.
   bit isPseudo = 1;

llvm/trunk/test/TableGen/FastISelEmitter.td

+// RUN: llvm-tblgen --gen-fast-isel -I %p/../../include %s 2>&1 | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+//===- Define the necessary boilerplate for our test target. --------------===//
+
+def MyTargetISA : InstrInfo;
+def MyTarget : Target { let InstructionSet = MyTargetISA; }
+
+def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
+def R1 : Register<"r0"> { let Namespace = "MyTarget"; }
+def GPR32M : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
+def GPR32MOp : RegisterOperand<GPR32M>;
+
+def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0, R1)>;
+def GPR32Op : RegisterOperand<GPR32>;
+
+class I<dag OOps, dag IOps, list<dag> Pat> : Instruction {
+  let Namespace = "MyTarget";
+  let OutOperandList = OOps;
+  let InOperandList = IOps;
+  let Pattern = Pat;
+}
+
+def HasA : Predicate<"Subtarget->hasA()">;
+
+let Predicates = [HasA] in {
+
+  def ADD : I<(outs GPR32Op:$rd), (ins GPR32Op:$rs, GPR32Op:$rt),
+              [(set GPR32Op:$rd, (add GPR32Op:$rs, GPR32Op:$rt))]>;
+
+  let FastISelShouldIgnore = 1 in
+    def ADD_M : I<(outs GPR32MOp:$rd), (ins GPR32MOp:$rs, GPR32MOp:$rt),
+                  [(set GPR32MOp:$rd, (add GPR32MOp:$rs, GPR32MOp:$rt))]>;
+}
+
+// CHECK-NOT: error: Duplicate predicate in FastISel table!

llvm/trunk/utils/TableGen/CodeGenInstruction.h

public:
     bool hasExtraDefRegAllocReq : 1;
     bool isCodeGenOnly : 1;
     bool isPseudo : 1;
     bool isRegSequence : 1;
     bool isExtractSubreg : 1;
     bool isInsertSubreg : 1;
     bool isConvergent : 1;
     bool hasNoSchedulingInfo : 1;
+    bool FastISelShouldIgnore : 1;
 
     std::string DeprecatedReason;
     bool HasComplexDeprecationPredicate;
 
     /// Are there any undefined flags?
     bool hasUndefFlags() const {
       return mayLoad_Unset || mayStore_Unset || hasSideEffects_Unset;
     }

llvm/trunk/utils/TableGen/CodeGenInstruction.cpp

CodeGenInstruction::CodeGenInstruction(Record *R)
   hasPostISelHook = R->getValueAsBit("hasPostISelHook");
   hasCtrlDep   = R->getValueAsBit("hasCtrlDep");
   isNotDuplicable = R->getValueAsBit("isNotDuplicable");
   isRegSequence = R->getValueAsBit("isRegSequence");
   isExtractSubreg = R->getValueAsBit("isExtractSubreg");
   isInsertSubreg = R->getValueAsBit("isInsertSubreg");
   isConvergent = R->getValueAsBit("isConvergent");
   hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
+  FastISelShouldIgnore = R->getValueAsBit("FastISelShouldIgnore");
 
   bool Unset;
   mayLoad      = R->getValueAsBitOrUnset("mayLoad", Unset);
   mayLoad_Unset = Unset;
   mayStore     = R->getValueAsBitOrUnset("mayStore", Unset);
   mayStore_Unset = Unset;
   hasSideEffects = R->getValueAsBitOrUnset("hasSideEffects", Unset);
   hasSideEffects_Unset = Unset;

llvm/trunk/utils/TableGen/FastISelEmitter.cpp

for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
     if (Dst->isLeaf()) continue;
     Record *Op = Dst->getOperator();
     if (!Op->isSubClassOf("Instruction"))
       continue;
     CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
     if (II.Operands.empty())
       continue;
 
+    // Allow instructions to be marked as unavailable for FastISel for
+    // certain cases, i.e. an ISA has two 'and' instruction which differ
+    // by what registers they can use but are otherwise identical for
+    // codegen purposes.
+    if (II.FastISelShouldIgnore)
+      continue;
+
     // For now, ignore multi-instruction patterns.
     bool MultiInsts = false;
     for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
       TreePatternNode *ChildOp = Dst->getChild(i);
       if (ChildOp->isLeaf())
         continue;
       if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
         MultiInsts = true;