[NFC] [Power] Fix instruction format for xsrqpi

[syzaara]

Summary

xsrqpi is currently using Z23Form_1. The instruction format is xsrqpi R,VRT,VRB,RMC.
Rathar than bits 11-15 being used for FRA, it should have bits 11-14 reserved and bit 15 for R.
This patch adds a new class Z23Form_4 to fix the instruction format.

[sfertile]

Minor nit: the instructions that use this class are either Z23Form_7 ( xsrqpxp) or Z23Form_8 (xsrqpi, xsrqpix). The structure is correct but I think we should stick with the naming that matches the instruction descriptions in the ISA.

llvm/lib/Target/PowerPC/PPCInstrFormats.td

2137 ↗

(On Diff #146348)

FRT --> VRT

2139 ↗

(On Diff #146348)

FRB --> VRB

[nemanjai]

In D46761#1096460, @sfertile wrote:

Minor nit: the instructions that use this class are either Z23Form_7 ( xsrqpxp) or Z23Form_8 (xsrqpi, xsrqpix). The structure is correct but I think we should stick with the naming that matches the instruction descriptions in the ISA.

I agree. Even though tblgen will correctly encode things using positional matching here, it's nice from a readability perspective if the operands are named in an expected way. Feel free to fix that on the commit though.

llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td

class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
   bit RC = 0;    // set by isDOT
 
   let Inst{6-10}  = FRT;
   let Inst{11-22} = idx;
   let Inst{23-30} = xo;
   let Inst{31}    = RC;
 }
 
+class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
+              InstrItinClass itin, list<dag> pattern>
+         : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<5> VRT;
+  bit R;
+  bits<5> VRB;
+  bits<2> idx;
+
+  let Pattern = pattern;
+
+  bit RC = 0;    // set by isDOT
+
+  let Inst{6-10}  = VRT;
+  let Inst{11-14} = 0;
+  let Inst{15} = R;
+  let Inst{16-20} = VRB;
+  let Inst{21-22} = idx;
+  let Inst{23-30} = xo;
+  let Inst{31}    = RC;
+}
+
 //===----------------------------------------------------------------------===//
 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
     : I<0, OOL, IOL, asmstr, NoItinerary> {
   let isCodeGenOnly = 1;
   let PPC64 = 0;
   let Pattern = pattern;
   let Inst{31-0} = 0;
   let hasNoSchedulingInfo = 1;
 }
 
 class PseudoXFormMemOp<dag OOL, dag IOL, string asmstr, list<dag> pattern>
     : Pseudo<OOL, IOL, asmstr, pattern>, XFormMemOp;
 

llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   // Pattern for matching Vector HP -> Vector SP intrinsic. Defined as a
   // separate pattern so that it can convert the input register class from
   // VRRC(v8i16) to VSRC.
   def : Pat<(v4f32 (int_ppc_vsx_xvcvhpsp v8i16:$A)),
             (v4f32 (XVCVHPSP (COPY_TO_REGCLASS $A, VSRC)))>;
 
   class Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc,
                                 list<dag> pattern>
-    : Z23Form_1<opcode, xo,
+    : Z23Form_8<opcode, xo,
                 (outs vrrc:$vT), (ins u1imm:$r, vrrc:$vB, u2imm:$rmc),
                 !strconcat(opc, " $r, $vT, $vB, $rmc"), IIC_VecFP, pattern> {
     let RC = ex;
   }
 
   // Round to Quad-Precision Integer [with Inexact]
   def XSRQPI   : Z23_VT5_R1_VB5_RMC2_EX1<63,  5, 0, "xsrqpi" , []>;
   def XSRQPIX  : Z23_VT5_R1_VB5_RMC2_EX1<63,  5, 1, "xsrqpix", []>;