[mips] Mark select instructions correctly

[atanasyan]

LGTM

lib/Target/Mips/MicroMipsInstrFPU.td

let AddedComplexity = 40 in {
   def : MipsPat<(f32 (fpround FGR64Opnd:$src)),
                 (CVT_S_D64_MM FGR64Opnd:$src)>, ISA_MICROMIPS, FGR_64;
   def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
                 (CVT_D64_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS, FGR_64;
   def : MipsPat<(f32 (fpround AFGR64Opnd:$src)),
                 (CVT_S_D32_MM AFGR64Opnd:$src)>, ISA_MICROMIPS, FGR_32;
   def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
                 (CVT_D32_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS, FGR_32;
+
+// Selects
+defm : MovzPats0<GPR32, FGR32, MOVZ_I_S_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>,
+       ISA_MICROMIPS32_NOT_MIPS32R6;
+defm : MovzPats1<GPR32, FGR32, MOVZ_I_S_MM, XOR_MM>,
+       ISA_MICROMIPS32_NOT_MIPS32R6;
+
+defm : MovnPats<GPR32, FGR32, MOVN_I_S_MM, XOR_MM>,
+       ISA_MICROMIPS32_NOT_MIPS32R6;
+
+defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32_MM, SLT_MM, SLTu_MM, SLTi_MM,
+                 SLTiu_MM>,
+       ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
+defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32_MM, XOR_MM>,
+       ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
+defm : MovnPats<GPR32, AFGR64, MOVN_I_D32_MM, XOR_MM>,
+       ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;

lib/Target/Mips/MicroMipsInstrInfo.td

MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
                       !strconcat(instr_asm, "\t$rt, $addr")> ;
 
 
   def SWM_MM  : StoreWordMultMM<"swm">, ISA_MICROMIPS;
   def LWM_MM  : LoadWordMultMM<"lwm">, ISA_MICROMIPS;
 
   /// Move Conditional
   def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
-                  NoItinerary>, ADD_FM_MM<0, 0x58>;
+                                     II_MOVZ>, ADD_FM_MM<0, 0x58>,
+                  ISA_MICROMIPS32_NOT_MIPS32R6;
   def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
-                  NoItinerary>, ADD_FM_MM<0, 0x18>;
-  def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
-                  CMov_F_I_FM_MM<0x25>;
-  def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
-                  CMov_F_I_FM_MM<0x5>;
+                                     II_MOVN>, ADD_FM_MM<0, 0x18>,
+                  ISA_MICROMIPS32_NOT_MIPS32R6;
+  def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
+                  CMov_F_I_FM_MM<0x25>, ISA_MICROMIPS32_NOT_MIPS32R6;
+  def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
+                  CMov_F_I_FM_MM<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6;
 
   /// Move to/from HI/LO
   def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
                 MTLO_FM_MM<0x0b5>;
   def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
                 MTLO_FM_MM<0x0f5>;
   def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
                 MFLO_FM_MM<0x035>;
defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM,
                   SLTiu_MM, ZERO>, ISA_MICROMIPS32_NOT_MIPS32R6;
 
 defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>;
 defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
 defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>;
 defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
 defm : SetgeImmPats<GPR32, XORi_MM, SLTi_MM, SLTiu_MM>;
 
+// Select patterns
+
+// Instantiation of conditional move patterns.
+defm : MovzPats0<GPR32, GPR32, MOVZ_I_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>,
+       ISA_MICROMIPS32_NOT_MIPS32R6;
+defm : MovzPats1<GPR32, GPR32, MOVZ_I_MM, XOR_MM>,
+       ISA_MICROMIPS32_NOT_MIPS32R6;
+defm : MovzPats2<GPR32, GPR32, MOVZ_I_MM, XORi_MM>,
+       ISA_MICROMIPS32_NOT_MIPS32R6;
+
+
+defm : MovnPats<GPR32, GPR32, MOVN_I_MM, XOR_MM>, INSN_MIPS4_32_NOT_32R6_64R6;
+
+// Instantiation of conditional move patterns.
+defm : MovzPats0<GPR32, GPR32, MOVZ_I_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>,
+       ISA_MICROMIPS32_NOT_MIPS32R6;
+defm : MovzPats1<GPR32, GPR32, MOVZ_I_MM, XOR_MM>,
+       ISA_MICROMIPS32_NOT_MIPS32R6;
+defm : MovzPats2<GPR32, GPR32, MOVZ_I_MM, XORi_MM>,
+       ISA_MICROMIPS32_NOT_MIPS32R6;
+
+defm : MovnPats<GPR32, GPR32, MOVN_I_MM, XOR_MM>, ISA_MICROMIPS32_NOT_MIPS32R6;
+
 //===----------------------------------------------------------------------===//
 // MicroMips instruction aliases
 //===----------------------------------------------------------------------===//
 
 class UncondBranchMMPseudo<string opstr> :
   MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
                     !strconcat(opstr, "\t$offset")>;
 

lib/Target/Mips/MipsCondMov.td

def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
                 (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
   def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
                 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
   def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
                 (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
 }
 
 // Instantiation of instructions.
+let AdditionalPredicates = [NotInMicroMips] in {
   def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>,
                  ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
 
   let isCodeGenOnly = 1 in {
     def MOVZ_I_I64   : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>,
                        ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
     def MOVZ_I64_I   : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>,
                        ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
     def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, II_MOVZ>,
                        ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
   }
 
   def MOVN_I_I       : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>,
                        ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
 
   let isCodeGenOnly = 1 in {
     def MOVN_I_I64   : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>,
                        ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
     def MOVN_I64_I   : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>,
                        ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
     def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>,
                        ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
   }
-let AdditionalPredicates = [NotInMicroMips] in {
   def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>,
                  CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
 
   let isCodeGenOnly = 1 in
   def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>,
                    CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
 
   def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>,
                  CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
 
   let isCodeGenOnly = 1 in
   def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
                    CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
 
   def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
                                       II_MOVZ_D>, CMov_I_F_FM<18, 17>,
                    INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
   def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
                                       II_MOVN_D>, CMov_I_F_FM<19, 17>,
                    INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
-}
+
   let DecoderNamespace = "MipsFP64" in {
     def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
                      CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
     def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
                      CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
     let isCodeGenOnly = 1 in {
       def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>,
                          CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
       def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>,
                          CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
     }
   }
 
   def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
                CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6;
 
   let isCodeGenOnly = 1 in
   def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>,
                  CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
 
   def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
                CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6;
 
   let isCodeGenOnly = 1 in
   def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,
                  CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
-let AdditionalPredicates = [NotInMicroMips] in {
   def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,
                CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6;
   def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,
                CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6;
 
   def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
                                     MipsCMovFP_T>, CMov_F_F_FM<17, 1>,
                  INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
   def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
                                     MipsCMovFP_F>, CMov_F_F_FM<17, 0>,
                  INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
-}
+
   let DecoderNamespace = "MipsFP64" in {
     def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
                    CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
     def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
                    CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
   }
 
   // Instantiation of conditional move patterns.
   defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
          INSN_MIPS4_32_NOT_32R6_64R6;
   defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
   defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>, INSN_MIPS4_32_NOT_32R6_64R6;
 
   defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
          INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
   defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,
          INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
   defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>,
          INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
   defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
          INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
   defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,
          INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
   defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>,
          INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
   defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,
          INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
   defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,
          INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
   defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>,
          INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
 
   defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
 
   defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
          GPR_64;
   defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
          GPR_64;
   defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
          GPR_64;
 
   defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
          INSN_MIPS4_32_NOT_32R6_64R6;
   defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
   defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
 
   defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>,
          INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
   defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
          GPR_64;
   defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
          GPR_64;
 
   defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
          INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
   defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
          FGR_32;
   defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
          FGR_32;
 
   defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
          INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
   defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64, SLTiu64>,
          INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
   defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
          FGR_64;
   defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>,
          INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
   defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
          FGR_64;
   defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
          FGR_64;
-
+}
 // For targets that don't have conditional-move instructions
 // we have to match SELECT nodes with pseudo instructions.
 let usesCustomInserter = 1 in {
   class Select_Pseudo<RegisterOperand RC> :
     PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
             [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,
     ISA_MIPS1_NOT_4_32;
 

test/CodeGen/Mips/llvm-ir/add.ll

; ALL-LABEL: add_i128_4:
   ; GP64-NOT-R2-R6: dsll    $[[T2:[0-9]+]], $[[T1]], 32
   ; GP64-NOT-R2-R6: dsrl    $[[T3:[0-9]+]], $[[T2]], 32
   ; GP64-R2-R6:     dext    $[[T3:[0-9]+]], $[[T1]], 0, 32
 
   ; GP64:           daddu   $2, $4, $[[T3]]
 
   ; MMR3:       addiur2 $[[T0:[0-9]+]], $7, 4
   ; MMR3:       sltu    $[[T1:[0-9]+]], $[[T0]], $7
-  ; MMR3:       sltu    $[[T2:[0-9]+]], $[[T0]], $7
-  ; MMR3:       addu16  $[[T3:[0-9]+]], $6, $[[T2]]
-  ; MMR3:       sltu    $[[T4:[0-9]+]], $[[T3]], $6
-  ; MMR3:       movz    $[[T4]], $[[T2]], $[[T1]]
-  ; MMR3:       addu16  $[[T6:[0-9]+]], $5, $[[T4]]
+  ; MMR3:       addu16  $[[T2:[0-9]+]], $6, $[[T1]]
+  ; MMR3:       sltu    $[[T3:[0-9]+]], $[[T2]], $6
+  ; MMR3:       movz    $[[T3]], $[[T1]], $[[T1]]
+  ; MMR3:       addu16  $[[T6:[0-9]+]], $5, $[[T3]]
   ; MMR3:       sltu    $[[T7:[0-9]+]], $[[T6]], $5
   ; MMR3:       addu16  $2, $4, $[[T7]]
 
   ; MMR6: addiur2 $[[T1:[0-9]+]], $7, 4
   ; MMR6: sltu    $[[T2:[0-9]+]], $[[T1]], $7
   ; MMR6: xori    $[[T3:[0-9]+]], $[[T2]], 1
   ; MMR6: selnez  $[[T4:[0-9]+]], $[[T2]], $[[T3]]
   ; MMR6: addu16  $[[T5:[0-9]+]], $6, $[[T2]]
; ALL-LABEL: add_i128_3:
   ; GP64-NOT-R2-R6: dsrl    $[[T3:[0-9]+]], $[[T2]], 32
   ; GP64-R2-R6:     dext    $[[T3:[0-9]+]], $[[T1]], 0, 32
 
   ; GP64:           daddu   $2, $4, $[[T3]]
 
   ; MMR3:       move    $[[T1:[0-9]+]], $7
   ; MMR3:       addius5 $[[T1]], 3
   ; MMR3:       sltu    $[[T2:[0-9]+]], $[[T1]], $7
-  ; MMR3:       sltu    $[[T3:[0-9]+]], $[[T1]], $7
-  ; MMR3:       addu16  $[[T4:[0-9]+]], $6, $[[T3]]
-  ; MMR3:       sltu    $[[T5:[0-9]+]], $[[T4]], $6
-  ; MMR3:       movz    $[[T5]], $[[T3]], $[[T2]]
-  ; MMR3:       addu16  $[[T6:[0-9]+]], $5, $[[T5]]
-  ; MMR3:       sltu    $[[T7:[0-9]+]], $[[T6]], $5
-  ; MMR3:       addu16  $2, $4, $[[T7]]
+  ; MMR3:       addu16  $[[T3:[0-9]+]], $6, $[[T2]]
+  ; MMR3:       sltu    $[[T4:[0-9]+]], $[[T3]], $6
+  ; MMR3:       movz    $[[T4]], $[[T2]], $[[T2]]
+  ; MMR3:       addu16  $[[T5:[0-9]+]], $5, $[[T4]]
+  ; MMR3:       sltu    $[[T6:[0-9]+]], $[[T5]], $5
+  ; MMR3:       addu16  $2, $4, $[[T6]]
 
   ; MMR6: move    $[[T1:[0-9]+]], $7
   ; MMR6: addius5 $[[T1]], 3
   ; MMR6: sltu    $[[T2:[0-9]+]], $[[T1]], $7
   ; MMR6: xori    $[[T3:[0-9]+]], $[[T2]], 1
   ; MMR6: selnez  $[[T4:[0-9]+]], $[[T2]], $[[T3]]
   ; MMR6: addu16  $[[T5:[0-9]+]], $6, $[[T2]]
   ; MMR6: sltu    $[[T6:[0-9]+]], $[[T5]], $6

test/CodeGen/Mips/llvm-ir/lshr.ll

 ; MIPS64R6-NEXT:    dsrlv $4, $4, $7
 ; MIPS64R6-NEXT:    selnez $3, $4, $2
 ; MIPS64R6-NEXT:    or $3, $3, $1
 ; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    seleqz $2, $4, $2
 ;
 ; MMR3-LABEL: lshr_i128:
 ; MMR3:       # %bb.0: # %entry
-; MMR3-NEXT:    addiusp -48
-; MMR3-NEXT:    .cfi_def_cfa_offset 48
-; MMR3-NEXT:    sw $17, 44($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    sw $16, 40($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    addiusp -40
+; MMR3-NEXT:    .cfi_def_cfa_offset 40
+; MMR3-NEXT:    sw $17, 36($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    sw $16, 32($sp) # 4-byte Folded Spill
 ; MMR3-NEXT:    .cfi_offset 17, -4
 ; MMR3-NEXT:    .cfi_offset 16, -8
 ; MMR3-NEXT:    move $8, $7
-; MMR3-NEXT:    sw $6, 32($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    sw $5, 36($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    sw $6, 24($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    sw $4, 28($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    lw $16, 68($sp)
+; MMR3-NEXT:    li16 $2, 64
+; MMR3-NEXT:    subu16 $7, $2, $16
+; MMR3-NEXT:    sllv $9, $5, $7
 ; MMR3-NEXT:    move $17, $5
-; MMR3-NEXT:    sw $4, 8($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    lw $16, 76($sp)
-; MMR3-NEXT:    srlv $7, $7, $16
+; MMR3-NEXT:    sw $5, 0($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    andi16 $3, $7, 32
+; MMR3-NEXT:    sw $3, 20($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    li16 $2, 0
+; MMR3-NEXT:    move $4, $9
+; MMR3-NEXT:    movn $4, $2, $3
+; MMR3-NEXT:    srlv $5, $8, $16
 ; MMR3-NEXT:    not16 $3, $16
-; MMR3-NEXT:    sw $3, 24($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    sw $3, 16($sp) # 4-byte Folded Spill
 ; MMR3-NEXT:    sll16 $2, $6, 1
-; MMR3-NEXT:    sllv $3, $2, $3
-; MMR3-NEXT:    li16 $4, 64
-; MMR3-NEXT:    or16 $3, $7
+; MMR3-NEXT:    sllv $2, $2, $3
+; MMR3-NEXT:    or16 $2, $5
 ; MMR3-NEXT:    srlv $5, $6, $16
-; MMR3-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    subu16 $7, $4, $16
-; MMR3-NEXT:    sllv $9, $17, $7
-; MMR3-NEXT:    andi16 $2, $7, 32
-; MMR3-NEXT:    sw $2, 28($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    andi16 $17, $16, 32
-; MMR3-NEXT:    sw $17, 16($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    move $4, $9
-; MMR3-NEXT:    li16 $6, 0
-; MMR3-NEXT:    movn $4, $6, $2
-; MMR3-NEXT:    movn $3, $5, $17
-; MMR3-NEXT:    addiu $2, $16, -64
-; MMR3-NEXT:    lw $5, 36($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    srlv $5, $5, $2
-; MMR3-NEXT:    sw $5, 20($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    lw $17, 8($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    sll16 $6, $17, 1
-; MMR3-NEXT:    sw $6, 4($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    not16 $5, $2
+; MMR3-NEXT:    sw $5, 4($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    andi16 $3, $16, 32
+; MMR3-NEXT:    sw $3, 12($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    movn $2, $5, $3
+; MMR3-NEXT:    addiu $3, $16, -64
+; MMR3-NEXT:    or16 $2, $4
+; MMR3-NEXT:    srlv $4, $17, $3
+; MMR3-NEXT:    sw $4, 8($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    lw $4, 28($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    sll16 $6, $4, 1
+; MMR3-NEXT:    not16 $5, $3
 ; MMR3-NEXT:    sllv $5, $6, $5
-; MMR3-NEXT:    or16 $3, $4
-; MMR3-NEXT:    lw $4, 20($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    or16 $5, $4
-; MMR3-NEXT:    srlv $1, $17, $2
-; MMR3-NEXT:    andi16 $2, $2, 32
-; MMR3-NEXT:    sw $2, 20($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    movn $5, $1, $2
-; MMR3-NEXT:    sllv $2, $17, $7
-; MMR3-NEXT:    not16 $4, $7
-; MMR3-NEXT:    lw $7, 36($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    srl16 $6, $7, 1
-; MMR3-NEXT:    srlv $4, $6, $4
-; MMR3-NEXT:    sltiu $11, $16, 64
-; MMR3-NEXT:    movn $5, $3, $11
+; MMR3-NEXT:    lw $17, 8($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    or16 $5, $17
+; MMR3-NEXT:    srlv $1, $4, $3
+; MMR3-NEXT:    andi16 $3, $3, 32
+; MMR3-NEXT:    sw $3, 8($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    movn $5, $1, $3
+; MMR3-NEXT:    sltiu $10, $16, 64
+; MMR3-NEXT:    movn $5, $2, $10
+; MMR3-NEXT:    sllv $2, $4, $7
+; MMR3-NEXT:    not16 $3, $7
+; MMR3-NEXT:    lw $7, 0($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    srl16 $4, $7, 1
+; MMR3-NEXT:    srlv $4, $4, $3
 ; MMR3-NEXT:    or16 $4, $2
 ; MMR3-NEXT:    srlv $2, $7, $16
-; MMR3-NEXT:    lw $3, 24($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    lw $6, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    lw $3, 16($sp) # 4-byte Folded Reload
 ; MMR3-NEXT:    sllv $3, $6, $3
 ; MMR3-NEXT:    or16 $3, $2
-; MMR3-NEXT:    srlv $2, $17, $16
-; MMR3-NEXT:    lw $6, 16($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    movn $3, $2, $6
-; MMR3-NEXT:    sltiu $10, $16, 64
+; MMR3-NEXT:    lw $2, 28($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    srlv $2, $2, $16
+; MMR3-NEXT:    lw $17, 12($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    movn $3, $2, $17
 ; MMR3-NEXT:    movz $5, $8, $16
+; MMR3-NEXT:    li16 $6, 0
+; MMR3-NEXT:    movz $3, $6, $10
+; MMR3-NEXT:    lw $7, 20($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    movn $4, $9, $7
+; MMR3-NEXT:    lw $6, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    li16 $7, 0
+; MMR3-NEXT:    movn $6, $7, $17
+; MMR3-NEXT:    or16 $6, $4
+; MMR3-NEXT:    lw $4, 8($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    movn $1, $7, $4
 ; MMR3-NEXT:    li16 $7, 0
-; MMR3-NEXT:    movz $3, $7, $10
-; MMR3-NEXT:    lw $17, 28($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    movn $4, $9, $17
-; MMR3-NEXT:    lw $7, 12($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    li16 $17, 0
-; MMR3-NEXT:    movn $7, $17, $6
-; MMR3-NEXT:    or16 $7, $4
-; MMR3-NEXT:    lw $4, 20($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    movn $1, $17, $4
-; MMR3-NEXT:    li16 $17, 0
-; MMR3-NEXT:    movn $1, $7, $11
-; MMR3-NEXT:    lw $4, 32($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    movn $1, $6, $10
+; MMR3-NEXT:    lw $4, 24($sp) # 4-byte Folded Reload
 ; MMR3-NEXT:    movz $1, $4, $16
-; MMR3-NEXT:    movn $2, $17, $6
+; MMR3-NEXT:    movn $2, $7, $17
 ; MMR3-NEXT:    li16 $4, 0
 ; MMR3-NEXT:    movz $2, $4, $10
 ; MMR3-NEXT:    move $4, $1
-; MMR3-NEXT:    lw $16, 40($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    lw $17, 44($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    addiusp 48
+; MMR3-NEXT:    lw $16, 32($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    lw $17, 36($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    addiusp 40
 ; MMR3-NEXT:    jrc $ra
 ;
 ; MMR6-LABEL: lshr_i128:
 ; MMR6:       # %bb.0: # %entry
 ; MMR6-NEXT:    addiu $sp, $sp, -32
 ; MMR6-NEXT:    .cfi_def_cfa_offset 32
 ; MMR6-NEXT:    sw $17, 28($sp) # 4-byte Folded Spill
 ; MMR6-NEXT:    sw $16, 24($sp) # 4-byte Folded Spill

test/CodeGen/Mips/llvm-ir/select-dbl.ll

 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
 ; RUN:    -check-prefix=CMOV64
 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
 ; RUN:    -check-prefix=CMOV64
 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
 ; RUN:    -check-prefix=CMOV64
 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
 ; RUN:    -check-prefix=64R6
-; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 \
+; RUN:   -asm-show-inst -mattr=+micromips -verify-machineinstrs | FileCheck %s \
 ; RUN:    -check-prefix=MM32R3
 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
 ; RUN:    -check-prefix=MM32R6
 
 define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
 ; M2-LABEL: tst_select_i1_double:
 ; M2:       # %bb.0: # %entry
 ; M2-NEXT:    andi $1, $4, 1

 ; 64R6-LABEL: tst_select_i1_double:
 ; 64R6:       # %bb.0: # %entry
 ; 64R6-NEXT:    mtc1 $4, $f0
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.d $f0, $f14, $f13
 ;
 ; MM32R3-LABEL: tst_select_i1_double:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mtc1 $7, $f2
-; MM32R3-NEXT:    mthc1 $6, $f2
-; MM32R3-NEXT:    andi16 $2, $4, 1
-; MM32R3-NEXT:    ldc1 $f0, 16($sp)
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movn.d $f0, $f2, $2
+; MM32R3:       mtc1 $7, $f2 # <MCInst #{{.*}} MTC1
+; MM32R3:       mthc1 $6, $f2 # <MCInst #{{.*}} MTHC1_D32_MM
+; MM32R3:       andi16 $2, $4, 1 # <MCInst #{{.*}} ANDI16_MM
+; MM32R3:       ldc1 $f0, 16($sp) # <MCInst #{{.*}} LDC1_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movn.d $f0, $f2, $2 # <MCInst #{{.*}} MOVN_I_D32_MM
 ;
 ; MM32R6-LABEL: tst_select_i1_double:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    mtc1 $7, $f1
 ; MM32R6-NEXT:    mthc1 $6, $f1
 ; MM32R6-NEXT:    mtc1 $4, $f0
 ; MM32R6-NEXT:    ldc1 $f2, 16($sp)
 ; MM32R6-NEXT:    sel.d $f0, $f2, $f1

 ; 64R6-LABEL: tst_select_i1_double_reordered:
 ; 64R6:       # %bb.0: # %entry
 ; 64R6-NEXT:    mtc1 $6, $f0
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.d $f0, $f13, $f12
 ;
 ; MM32R3-LABEL: tst_select_i1_double_reordered:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mov.d $f0, $f14
-; MM32R3-NEXT:    lw $2, 16($sp)
-; MM32R3-NEXT:    andi16 $2, $2, 1
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movn.d $f0, $f12, $2
+; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
+; MM32R3:       lw $2, 16($sp) # <MCInst #{{.*}} LWSP_MM
+; MM32R3:       andi16 $2, $2, 1 # <MCInst #{{.*}} ANDI16_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movn.d $f0, $f12, $2 # <MCInst #{{.*}} MOVN_I_D32_MM
 ;
 ; MM32R6-LABEL: tst_select_i1_double_reordered:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    lw $1, 16($sp)
 ; MM32R6-NEXT:    mtc1 $1, $f0
 ; MM32R6-NEXT:    sel.d $f0, $f14, $f12
 ; MM32R6-NEXT:    jrc $ra
                                               i1 signext %s) {

 ; 64R6-NEXT:    cmp.lt.d $f0, $f12, $f13
 ; 64R6-NEXT:    mfc1 $1, $f0
 ; 64R6-NEXT:    mtc1 $1, $f0
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.d $f0, $f13, $f12
 ;
 ; MM32R3-LABEL: tst_select_fcmp_olt_double:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mov.d $f0, $f14
-; MM32R3-NEXT:    c.olt.d $f12, $f14
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movt.d $f0, $f12, $fcc0
+; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
+; MM32R3:       c.olt.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movt.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_D32_MM
 ;
 ; MM32R6-LABEL: tst_select_fcmp_olt_double:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    cmp.lt.d $f0, $f12, $f14
 ; MM32R6-NEXT:    mfc1 $1, $f0
 ; MM32R6-NEXT:    mtc1 $1, $f0
 ; MM32R6-NEXT:    sel.d $f0, $f14, $f12
 ; MM32R6-NEXT:    jrc $ra

 ; 64R6-NEXT:    cmp.le.d $f0, $f12, $f13
 ; 64R6-NEXT:    mfc1 $1, $f0
 ; 64R6-NEXT:    mtc1 $1, $f0
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.d $f0, $f13, $f12
 ;
 ; MM32R3-LABEL: tst_select_fcmp_ole_double:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mov.d $f0, $f14
-; MM32R3-NEXT:    c.ole.d $f12, $f14
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movt.d $f0, $f12, $fcc0
+; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
+; MM32R3:       c.ole.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movt.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_D32_MM
 ;
 ; MM32R6-LABEL: tst_select_fcmp_ole_double:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    cmp.le.d $f0, $f12, $f14
 ; MM32R6-NEXT:    mfc1 $1, $f0
 ; MM32R6-NEXT:    mtc1 $1, $f0
 ; MM32R6-NEXT:    sel.d $f0, $f14, $f12
 ; MM32R6-NEXT:    jrc $ra

 ; 64R6-NEXT:    cmp.lt.d $f0, $f13, $f12
 ; 64R6-NEXT:    mfc1 $1, $f0
 ; 64R6-NEXT:    mtc1 $1, $f0
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.d $f0, $f13, $f12
 ;
 ; MM32R3-LABEL: tst_select_fcmp_ogt_double:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mov.d $f0, $f14
-; MM32R3-NEXT:    c.ule.d $f12, $f14
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movf.d $f0, $f12, $fcc0
+; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
+; MM32R3:       c.ule.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movf.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_D32_MM
 ;
 ; MM32R6-LABEL: tst_select_fcmp_ogt_double:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    cmp.lt.d $f0, $f14, $f12
 ; MM32R6-NEXT:    mfc1 $1, $f0
 ; MM32R6-NEXT:    mtc1 $1, $f0
 ; MM32R6-NEXT:    sel.d $f0, $f14, $f12
 ; MM32R6-NEXT:    jrc $ra

 ; 64R6-NEXT:    cmp.le.d $f0, $f13, $f12
 ; 64R6-NEXT:    mfc1 $1, $f0
 ; 64R6-NEXT:    mtc1 $1, $f0
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.d $f0, $f13, $f12
 ;
 ; MM32R3-LABEL: tst_select_fcmp_oge_double:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mov.d $f0, $f14
-; MM32R3-NEXT:    c.ult.d $f12, $f14
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movf.d $f0, $f12, $fcc0
+; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
+; MM32R3:       c.ult.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movf.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_D32_MM
 ;
 ; MM32R6-LABEL: tst_select_fcmp_oge_double:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    cmp.le.d $f0, $f14, $f12
 ; MM32R6-NEXT:    mfc1 $1, $f0
 ; MM32R6-NEXT:    mtc1 $1, $f0
 ; MM32R6-NEXT:    sel.d $f0, $f14, $f12
 ; MM32R6-NEXT:    jrc $ra

 ; 64R6-NEXT:    cmp.eq.d $f0, $f12, $f13
 ; 64R6-NEXT:    mfc1 $1, $f0
 ; 64R6-NEXT:    mtc1 $1, $f0
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.d $f0, $f13, $f12
 ;
 ; MM32R3-LABEL: tst_select_fcmp_oeq_double:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mov.d $f0, $f14
-; MM32R3-NEXT:    c.eq.d $f12, $f14
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movt.d $f0, $f12, $fcc0
+; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
+; MM32R3:       c.eq.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movt.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_D32_MM
 ;
 ; MM32R6-LABEL: tst_select_fcmp_oeq_double:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    cmp.eq.d $f0, $f12, $f14
 ; MM32R6-NEXT:    mfc1 $1, $f0
 ; MM32R6-NEXT:    mtc1 $1, $f0
 ; MM32R6-NEXT:    sel.d $f0, $f14, $f12
 ; MM32R6-NEXT:    jrc $ra

 ; 64R6-NEXT:    mfc1 $1, $f0
 ; 64R6-NEXT:    not $1, $1
 ; 64R6-NEXT:    mtc1 $1, $f0
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.d $f0, $f13, $f12
 ;
 ; MM32R3-LABEL: tst_select_fcmp_one_double:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mov.d $f0, $f14
-; MM32R3-NEXT:    c.ueq.d $f12, $f14
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movf.d $f0, $f12, $fcc0
+; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
+; MM32R3:       c.ueq.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movf.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_D32_MM
 ;
 ; MM32R6-LABEL: tst_select_fcmp_one_double:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    cmp.ueq.d $f0, $f12, $f14
 ; MM32R6-NEXT:    mfc1 $1, $f0
 ; MM32R6-NEXT:    not $1, $1
 ; MM32R6-NEXT:    mtc1 $1, $f0
 ; MM32R6-NEXT:    sel.d $f0, $f14, $f12
 ; MM32R6-NEXT:    jrc $ra
 entry:
   %s = fcmp one double %x, %y
   %r = select i1 %s, double %x, double %y
   ret double %r
 }

test/CodeGen/Mips/llvm-ir/select-flt.ll

 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
 ; RUN:    -check-prefixes=CMOV64
 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
 ; RUN:    -check-prefixes=CMOV64
 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
 ; RUN:    -check-prefixes=CMOV64
 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
 ; RUN:    -check-prefixes=64R6
-; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs -asm-show-inst | FileCheck %s \
 ; RUN:    -check-prefixes=MM32R3
 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
 ; RUN:    -check-prefixes=MM32R6
 
 define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
 ; M2-LABEL: tst_select_i1_float:
 ; M2:       # %bb.0: # %entry
 ; M2-NEXT:    andi $1, $4, 1

 ; 64R6-LABEL: tst_select_i1_float:
 ; 64R6:       # %bb.0: # %entry
 ; 64R6-NEXT:    mtc1 $4, $f0
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.s $f0, $f14, $f13
 ;
 ; MM32R3-LABEL: tst_select_i1_float:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mtc1 $6, $f0
-; MM32R3-NEXT:    andi16 $2, $4, 1
-; MM32R3-NEXT:    mtc1 $5, $f1
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movn.s $f0, $f1, $2
+; MM32R3:       mtc1 $6, $f0 # <MCInst #{{.*}} MTC1_MM
+; MM32R3:       andi16 $2, $4, 1 # <MCInst #{{.*}} ANDI16_MM
+; MM32R3:       mtc1 $5, $f1 # <MCInst #{{.*}} MTC1_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movn.s $f0, $f1, $2 # <MCInst #{{.*}} MOVN_I_S_MM
 ;
 ; MM32R6-LABEL: tst_select_i1_float:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    mtc1 $5, $f1
 ; MM32R6-NEXT:    mtc1 $6, $f2
 ; MM32R6-NEXT:    mtc1 $4, $f0
 ; MM32R6-NEXT:    sel.s $f0, $f2, $f1
 ; MM32R6-NEXT:    jrc $ra

 ; 64R6-LABEL: tst_select_i1_float_reordered:
 ; 64R6:       # %bb.0: # %entry
 ; 64R6-NEXT:    mtc1 $6, $f0
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.s $f0, $f13, $f12
 ;
 ; MM32R3-LABEL: tst_select_i1_float_reordered:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mov.s $f0, $f14
-; MM32R3-NEXT:    andi16 $2, $6, 1
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movn.s $f0, $f12, $2
+; MM32R3:       mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S
+; MM32R3:       andi16 $2, $6, 1 # <MCInst #{{.*}} ANDI16_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movn.s $f0, $f12, $2 # <MCInst #{{.*}} MOVN_I_S_MM
 ;
 ; MM32R6-LABEL: tst_select_i1_float_reordered:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    mtc1 $6, $f0
 ; MM32R6-NEXT:    sel.s $f0, $f14, $f12
 ; MM32R6-NEXT:    jrc $ra
                                             i1 signext %s) {
 entry:

 ; 64R6-LABEL: tst_select_fcmp_olt_float:
 ; 64R6:       # %bb.0: # %entry
 ; 64R6-NEXT:    cmp.lt.s $f0, $f12, $f13
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.s $f0, $f13, $f12
 ;
 ; MM32R3-LABEL: tst_select_fcmp_olt_float:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mov.s $f0, $f14
-; MM32R3-NEXT:    c.olt.s $f12, $f14
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movt.s $f0, $f12, $fcc0
+; MM32R3:       mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S
+; MM32R3:       c.olt.s $f12, $f14 # <MCInst #{{.*}} FCMP_S32_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movt.s $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_S_MM
 ;
 ; MM32R6-LABEL: tst_select_fcmp_olt_float:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    cmp.lt.s $f0, $f12, $f14
 ; MM32R6-NEXT:    sel.s $f0, $f14, $f12
 ; MM32R6-NEXT:    jrc $ra
 entry:
   %s = fcmp olt float %x, %y

 ; 64R6-LABEL: tst_select_fcmp_ole_float:
 ; 64R6:       # %bb.0: # %entry
 ; 64R6-NEXT:    cmp.le.s $f0, $f12, $f13
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.s $f0, $f13, $f12
 ;
 ; MM32R3-LABEL: tst_select_fcmp_ole_float:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mov.s $f0, $f14
-; MM32R3-NEXT:    c.ole.s $f12, $f14
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movt.s $f0, $f12, $fcc0
+; MM32R3:       mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S
+; MM32R3:       c.ole.s $f12, $f14 # <MCInst #{{.*}} FCMP_S32_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movt.s $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_S_MM
 ;
 ; MM32R6-LABEL: tst_select_fcmp_ole_float:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    cmp.le.s $f0, $f12, $f14
 ; MM32R6-NEXT:    sel.s $f0, $f14, $f12
 ; MM32R6-NEXT:    jrc $ra
 entry:
   %s = fcmp ole float %x, %y

 ; 64R6-LABEL: tst_select_fcmp_ogt_float:
 ; 64R6:       # %bb.0: # %entry
 ; 64R6-NEXT:    cmp.lt.s $f0, $f13, $f12
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.s $f0, $f13, $f12
 ;
 ; MM32R3-LABEL: tst_select_fcmp_ogt_float:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mov.s $f0, $f14
-; MM32R3-NEXT:    c.ule.s $f12, $f14
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movf.s $f0, $f12, $fcc0
+; MM32R3:       mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S
+; MM32R3:       c.ule.s $f12, $f14 # <MCInst #{{.*}} FCMP_S32_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movf.s $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_S_MM
 ;
 ; MM32R6-LABEL: tst_select_fcmp_ogt_float:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    cmp.lt.s $f0, $f14, $f12
 ; MM32R6-NEXT:    sel.s $f0, $f14, $f12
 ; MM32R6-NEXT:    jrc $ra
 entry:
   %s = fcmp ogt float %x, %y

 ; 64R6-LABEL: tst_select_fcmp_oge_float:
 ; 64R6:       # %bb.0: # %entry
 ; 64R6-NEXT:    cmp.le.s $f0, $f13, $f12
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.s $f0, $f13, $f12
 ;
 ; MM32R3-LABEL: tst_select_fcmp_oge_float:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mov.s $f0, $f14
-; MM32R3-NEXT:    c.ult.s $f12, $f14
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movf.s $f0, $f12, $fcc0
+; MM32R3:       mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S
+; MM32R3:       c.ult.s $f12, $f14 # <MCInst #{{.*}} FCMP_S32_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movf.s $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_S_MM
 ;
 ; MM32R6-LABEL: tst_select_fcmp_oge_float:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    cmp.le.s $f0, $f14, $f12
 ; MM32R6-NEXT:    sel.s $f0, $f14, $f12
 ; MM32R6-NEXT:    jrc $ra
 entry:
   %s = fcmp oge float %x, %y

 ; 64R6-LABEL: tst_select_fcmp_oeq_float:
 ; 64R6:       # %bb.0: # %entry
 ; 64R6-NEXT:    cmp.eq.s $f0, $f12, $f13
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.s $f0, $f13, $f12
 ;
 ; MM32R3-LABEL: tst_select_fcmp_oeq_float:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mov.s $f0, $f14
-; MM32R3-NEXT:    c.eq.s $f12, $f14
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movt.s $f0, $f12, $fcc0
+; MM32R3:       mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S
+; MM32R3:       c.eq.s $f12, $f14 # <MCInst #{{.*}} FCMP_S32_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movt.s $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_S_MM
 ;
 ; MM32R6-LABEL: tst_select_fcmp_oeq_float:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    cmp.eq.s $f0, $f12, $f14
 ; MM32R6-NEXT:    sel.s $f0, $f14, $f12
 ; MM32R6-NEXT:    jrc $ra
 entry:
   %s = fcmp oeq float %x, %y

 ; 64R6-NEXT:    mfc1 $1, $f0
 ; 64R6-NEXT:    not $1, $1
 ; 64R6-NEXT:    mtc1 $1, $f0
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    sel.s $f0, $f13, $f12
 ;
 ; MM32R3-LABEL: tst_select_fcmp_one_float:
 ; MM32R3:       # %bb.0: # %entry
-; MM32R3-NEXT:    mov.s $f0, $f14
-; MM32R3-NEXT:    c.ueq.s $f12, $f14
-; MM32R3-NEXT:    jr $ra
-; MM32R3-NEXT:    movf.s $f0, $f12, $fcc0
+; MM32R3:       mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S
+; MM32R3:       c.ueq.s $f12, $f14 # <MCInst #{{.*}} FCMP_S32_MM
+; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
+; MM32R3:       movf.s $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_S_MM
 ;
 ; MM32R6-LABEL: tst_select_fcmp_one_float:
 ; MM32R6:       # %bb.0: # %entry
 ; MM32R6-NEXT:    cmp.ueq.s $f0, $f12, $f14
 ; MM32R6-NEXT:    mfc1 $1, $f0
 ; MM32R6-NEXT:    not $1, $1
 ; MM32R6-NEXT:    mtc1 $1, $f0
 ; MM32R6-NEXT:    sel.s $f0, $f14, $f12
 ; MM32R6-NEXT:    jrc $ra
 entry:
   %s = fcmp one float %x, %y
   %r = select i1 %s, float %x, float %y
   ret float %r
 }

test/CodeGen/Mips/llvm-ir/select-int.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,CMOV,CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,CMOV,CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,CMOV,CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,SEL,SEL-64
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM32R3
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM32R6
 
 define signext i1 @tst_select_i1_i1(i1 signext %s,
                                     i1 signext %x, i1 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i1:
entry:
   ; CMOV:   move    $2, $6
 
   ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
   ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
   ; SEL:    or      $2, $[[T2]], $[[T1]]
 
   ; MM32R3:   andi16  $[[T0:[0-9]+]], $4, 1
-  ; MM32R3:   movn    $[[T1:[0-9]+]], $5, $[[T0]]
+  ; MM32R3:   movn    $[[T1:[0-9]+]], $5, $[[T0]]  # <MCInst #{{[0-9]+}} MOVN_I_MM
   ; MM32R3:   move    $2, $[[T1]]
 
   ; MMR6:     andi16  $[[T0:[0-9]+]], $4, 1
   ; MMR6:     seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; MMR6:     selnez  $[[T2:[0-9]+]], $5, $[[T0]]
   ; MMR6:     or      $2, $[[T2]], $[[T1]]
 
   %r = select i1 %s, i1 %x, i1 %y
entry:
   ; CMOV:   move    $2, $6
 
   ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
   ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
   ; SEL:    or      $2, $[[T2]], $[[T1]]
 
   ; MM32R3:   andi16  $[[T0:[0-9]+]], $4, 1
-  ; MM32R3:   movn    $[[T1:[0-9]+]], $5, $[[T0]]
+  ; MM32R3:   movn    $[[T1:[0-9]+]], $5, $[[T0]]  # <MCInst #{{[0-9]+}} MOVN_I_MM
   ; MM32R3:   move    $2, $[[T1]]
 
   ; MMR6:     andi16  $[[T0:[0-9]+]], $4, 1
   ; MMR6:     seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; MMR6:     selnez  $[[T2:[0-9]+]], $5, $[[T0]]
   ; MMR6:     or      $2, $[[T2]], $[[T1]]
 
   %r = select i1 %s, i8 %x, i8 %y
entry:
   ; CMOV:   move    $2, $6
 
   ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
   ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
   ; SEL:    or      $2, $[[T2]], $[[T1]]
 
   ; MM32R3:     andi16  $[[T0:[0-9]+]], $4, 1
-  ; MM32R3:     movn    $[[T1:[0-9]+]], $5, $[[T0]]
+  ; MM32R3:     movn    $[[T1:[0-9]+]], $5, $[[T0]]  # <MCInst #{{[0-9]+}} MOVN_I_MM
   ; MM32R3:     move    $2, $[[T1]]
 
   ; MMR6:       andi16  $[[T0:[0-9]+]], $4, 1
   ; MMR6:       seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; MMR6:       selnez  $[[T2:[0-9]+]], $5, $[[T0]]
   ; MMR6:       or      $2, $[[T2]], $[[T1]]
 
   %r = select i1 %s, i32 %x, i32 %y
entry:
   ; FIXME: This shift is redundant
   ; SEL-64:     sll     $[[T0]], $[[T0]], 0
   ; SEL-64:     seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL-64:     selnez  $[[T0]], $5, $[[T0]]
   ; SEL-64:     or      $2, $[[T0]], $[[T1]]
 
   ; MM32R3:     andi16  $[[T0:[0-9]+]], $4, 1
   ; MM32R3:     lw      $2, 16($sp)
-  ; MM32R3:     movn    $2, $6, $[[T0]]
+  ; MM32R3:     movn    $2, $6, $[[T0]]  # <MCInst #{{[0-9]+}} MOVN_I_MM
   ; MM32R3:     lw      $3, 20($sp)
-  ; MM32R3:     movn    $3, $7, $[[T0]]
+  ; MM32R3:     movn    $3, $7, $[[T0]]  # <MCInst #{{[0-9]+}} MOVN_I_MM
 
   ; MM32R6:     andi16  $[[T0:[0-9]+]], $4, 1
   ; MM32R6:     lw      $[[T2:[0-9]+]], 16($sp)
   ; MM32R6:     seleqz  $[[T3:[0-9]+]], $[[T2]], $[[T0]]
   ; MM32R6:     selnez  $[[T1:[0-9]+]], $6, $[[T0]]
   ; MM32R6:     or      $2, $[[T1]], $[[T3]]
   ; MM32R6:     lw      $[[T4:[0-9]+]], 20($sp)
   ; MM32R6:     seleqz  $[[T5:[0-9]+]], $[[T4]], $[[T0]]
define i8* @tst_select_word_cst(i8* %a, i8* %b) {
   ; SEL-64:     sltu    $[[T2:[0-9]+]], $zero, $[[T1]]
   ; FIXME: This shift is redundant.
   ; SEL-64:     sll     $[[T2]], $[[T2]], 0
   ; SEL-64:     seleqz  $2, $4, $[[T2]]
 
   ; MM32R3:     li16    $[[T0:[0-9]+]], -1
   ; MM32R3:     xor     $[[T1:[0-9]+]], $5, $[[T0]]
   ; MM32R3:     li16    $[[T2:[0-9]+]], 0
-  ; MM32R3:     movn    $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; MM32R3:     movn    $[[T3:[0-9]+]], $[[T2]], $[[T1]]  # <MCInst #{{[0-9]+}} MOVN_I_MM
   ; MM32R3:     move    $2, $[[T3]]
 
   ; MM32R6:     li16    $[[T0:[0-9]+]], -1
   ; MM32R6:     xor     $[[T1:[0-9]+]], $5, $[[T0]]
   ; MM32R6:     sltu    $[[T2:[0-9]+]], $zero, $[[T1]]
   ; MM32R6:     seleqz  $2, $4, $[[T2]]
 
   %cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*)
   %r = select i1 %cmp, i8* %a, i8* null
   ret i8* %r
 }

test/CodeGen/Mips/llvm-ir/shl.ll

 ; MIPS64R6-NEXT:    dsllv $4, $5, $7
 ; MIPS64R6-NEXT:    selnez $2, $4, $3
 ; MIPS64R6-NEXT:    or $2, $2, $1
 ; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    seleqz $3, $4, $3
 ;
 ; MMR3-LABEL: shl_i128:
 ; MMR3:       # %bb.0: # %entry
-; MMR3-NEXT:    addiusp -48
-; MMR3-NEXT:    .cfi_def_cfa_offset 48
-; MMR3-NEXT:    sw $17, 44($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    sw $16, 40($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    addiusp -40
+; MMR3-NEXT:    .cfi_def_cfa_offset 40
+; MMR3-NEXT:    sw $17, 36($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    sw $16, 32($sp) # 4-byte Folded Spill
 ; MMR3-NEXT:    .cfi_offset 17, -4
 ; MMR3-NEXT:    .cfi_offset 16, -8
-; MMR3-NEXT:    sw $7, 8($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    sw $6, 36($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    move $17, $6
-; MMR3-NEXT:    sw $5, 32($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    move $17, $7
+; MMR3-NEXT:    sw $7, 4($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    move $7, $6
 ; MMR3-NEXT:    move $1, $4
-; MMR3-NEXT:    lw $16, 76($sp)
-; MMR3-NEXT:    sllv $2, $4, $16
-; MMR3-NEXT:    not16 $4, $16
+; MMR3-NEXT:    lw $16, 68($sp)
+; MMR3-NEXT:    li16 $2, 64
+; MMR3-NEXT:    subu16 $6, $2, $16
+; MMR3-NEXT:    srlv $9, $7, $6
+; MMR3-NEXT:    andi16 $4, $6, 32
 ; MMR3-NEXT:    sw $4, 24($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    srl16 $3, $5, 1
-; MMR3-NEXT:    srlv $4, $3, $4
-; MMR3-NEXT:    li16 $3, 64
-; MMR3-NEXT:    or16 $4, $2
-; MMR3-NEXT:    sllv $6, $5, $16
-; MMR3-NEXT:    sw $6, 20($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    subu16 $7, $3, $16
-; MMR3-NEXT:    srlv $9, $17, $7
-; MMR3-NEXT:    andi16 $2, $7, 32
-; MMR3-NEXT:    sw $2, 28($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    andi16 $3, $16, 32
-; MMR3-NEXT:    sw $3, 12($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    move $5, $9
-; MMR3-NEXT:    li16 $17, 0
-; MMR3-NEXT:    movn $5, $17, $2
-; MMR3-NEXT:    movn $4, $6, $3
-; MMR3-NEXT:    addiu $2, $16, -64
-; MMR3-NEXT:    lw $3, 36($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    sllv $3, $3, $2
+; MMR3-NEXT:    li16 $3, 0
+; MMR3-NEXT:    move $2, $9
+; MMR3-NEXT:    movn $2, $3, $4
+; MMR3-NEXT:    sllv $3, $1, $16
 ; MMR3-NEXT:    sw $3, 16($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    lw $17, 8($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    srl16 $6, $17, 1
-; MMR3-NEXT:    sw $6, 4($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    not16 $3, $2
-; MMR3-NEXT:    srlv $3, $6, $3
-; MMR3-NEXT:    or16 $4, $5
-; MMR3-NEXT:    lw $5, 16($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    or16 $3, $5
-; MMR3-NEXT:    sllv $8, $17, $2
-; MMR3-NEXT:    andi16 $2, $2, 32
-; MMR3-NEXT:    sw $2, 16($sp) # 4-byte Folded Spill
-; MMR3-NEXT:    movn $3, $8, $2
-; MMR3-NEXT:    srlv $2, $17, $7
-; MMR3-NEXT:    not16 $5, $7
-; MMR3-NEXT:    lw $7, 36($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    sll16 $6, $7, 1
-; MMR3-NEXT:    sllv $5, $6, $5
+; MMR3-NEXT:    not16 $4, $16
+; MMR3-NEXT:    sw $4, 20($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    sw $5, 28($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    srl16 $3, $5, 1
+; MMR3-NEXT:    srlv $3, $3, $4
+; MMR3-NEXT:    lw $4, 16($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    or16 $3, $4
+; MMR3-NEXT:    sllv $5, $5, $16
+; MMR3-NEXT:    sw $5, 8($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    andi16 $4, $16, 32
+; MMR3-NEXT:    sw $4, 16($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    movn $3, $5, $4
+; MMR3-NEXT:    addiu $4, $16, -64
+; MMR3-NEXT:    or16 $3, $2
+; MMR3-NEXT:    sllv $2, $7, $4
+; MMR3-NEXT:    sw $2, 12($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    srl16 $5, $17, 1
+; MMR3-NEXT:    not16 $2, $4
+; MMR3-NEXT:    srlv $2, $5, $2
+; MMR3-NEXT:    lw $17, 12($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    or16 $2, $17
+; MMR3-NEXT:    lw $17, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    sllv $8, $17, $4
+; MMR3-NEXT:    andi16 $4, $4, 32
+; MMR3-NEXT:    sw $4, 12($sp) # 4-byte Folded Spill
+; MMR3-NEXT:    movn $2, $8, $4
 ; MMR3-NEXT:    sltiu $10, $16, 64
-; MMR3-NEXT:    movn $3, $4, $10
-; MMR3-NEXT:    or16 $5, $2
-; MMR3-NEXT:    sllv $2, $7, $16
-; MMR3-NEXT:    lw $4, 24($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    lw $6, 4($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    srlv $4, $6, $4
-; MMR3-NEXT:    or16 $4, $2
+; MMR3-NEXT:    movn $2, $3, $10
+; MMR3-NEXT:    srlv $4, $17, $6
+; MMR3-NEXT:    not16 $3, $6
+; MMR3-NEXT:    sll16 $6, $7, 1
+; MMR3-NEXT:    sllv $3, $6, $3
+; MMR3-NEXT:    or16 $3, $4
+; MMR3-NEXT:    sllv $6, $7, $16
+; MMR3-NEXT:    lw $4, 20($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    srlv $4, $5, $4
+; MMR3-NEXT:    or16 $4, $6
 ; MMR3-NEXT:    sllv $6, $17, $16
-; MMR3-NEXT:    lw $2, 12($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    movn $4, $6, $2
-; MMR3-NEXT:    sltiu $11, $16, 64
-; MMR3-NEXT:    movz $3, $1, $16
-; MMR3-NEXT:    li16 $7, 0
-; MMR3-NEXT:    movz $4, $7, $11
-; MMR3-NEXT:    lw $17, 28($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    movn $5, $9, $17
-; MMR3-NEXT:    lw $7, 20($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    li16 $17, 0
-; MMR3-NEXT:    movn $7, $17, $2
-; MMR3-NEXT:    or16 $7, $5
-; MMR3-NEXT:    lw $5, 16($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    movn $8, $17, $5
-; MMR3-NEXT:    li16 $17, 0
-; MMR3-NEXT:    movn $8, $7, $10
-; MMR3-NEXT:    lw $5, 32($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    movz $8, $5, $16
-; MMR3-NEXT:    movn $6, $17, $2
+; MMR3-NEXT:    lw $17, 16($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    movn $4, $6, $17
+; MMR3-NEXT:    movz $2, $1, $16
 ; MMR3-NEXT:    li16 $5, 0
-; MMR3-NEXT:    movz $6, $5, $11
-; MMR3-NEXT:    move $2, $3
+; MMR3-NEXT:    movz $4, $5, $10
+; MMR3-NEXT:    lw $7, 24($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    movn $3, $9, $7
+; MMR3-NEXT:    lw $5, 8($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    li16 $7, 0
+; MMR3-NEXT:    movn $5, $7, $17
+; MMR3-NEXT:    or16 $5, $3
+; MMR3-NEXT:    lw $3, 12($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    movn $8, $7, $3
+; MMR3-NEXT:    li16 $7, 0
+; MMR3-NEXT:    movn $8, $5, $10
+; MMR3-NEXT:    lw $3, 28($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    movz $8, $3, $16
+; MMR3-NEXT:    movn $6, $7, $17
+; MMR3-NEXT:    li16 $3, 0
+; MMR3-NEXT:    movz $6, $3, $10
 ; MMR3-NEXT:    move $3, $8
 ; MMR3-NEXT:    move $5, $6
-; MMR3-NEXT:    lw $16, 40($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    lw $17, 44($sp) # 4-byte Folded Reload
-; MMR3-NEXT:    addiusp 48
+; MMR3-NEXT:    lw $16, 32($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    lw $17, 36($sp) # 4-byte Folded Reload
+; MMR3-NEXT:    addiusp 40
 ; MMR3-NEXT:    jrc $ra
 ;
 ; MMR6-LABEL: shl_i128:
 ; MMR6:       # %bb.0: # %entry
 ; MMR6-NEXT:    addiu $sp, $sp, -16
 ; MMR6-NEXT:    .cfi_def_cfa_offset 16
 ; MMR6-NEXT:    sw $17, 12($sp) # 4-byte Folded Spill
 ; MMR6-NEXT:    sw $16, 8($sp) # 4-byte Folded Spill

test/MC/Mips/micromips-movcond-instructions.s

-# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips \
+# RUN: llvm-mc %s -triple=mipsel -show-encoding -show-inst -mattr=micromips \
 # RUN: | FileCheck -check-prefix=CHECK-EL %s
-# RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips \
+# RUN: llvm-mc %s -triple=mips -show-encoding -show-inst -mattr=micromips \
 # RUN: | FileCheck -check-prefix=CHECK-EB %s
 # Check that the assembler can handle the documented syntax
 # for move conditional instructions.
 #------------------------------------------------------------------------------
 # Move Conditional
 #------------------------------------------------------------------------------
 # Little endian
 #------------------------------------------------------------------------------
 # CHECK-EL: movz    $9, $6, $7        # encoding: [0xe6,0x00,0x58,0x48]
+# CHECK-EL-NEXT:                      # <MCInst #{{[0-9]+}} MOVZ_I_MM
 # CHECK-EL: movn    $9, $6, $7        # encoding: [0xe6,0x00,0x18,0x48]
+# CHECK-EL-NEXT:                      # <MCInst #{{[0-9]+}} MOVN_I_MM
 # CHECK-EL: movt    $9, $6, $fcc0     # encoding: [0x26,0x55,0x7b,0x09]
+# CHECK-EL-NEXT:                      # <MCInst #{{[0-9]+}} MOVT_I_MM
 # CHECK-EL: movf    $9, $6, $fcc0     # encoding: [0x26,0x55,0x7b,0x01]
+# CHECK-EL-NEXT:                      # <MCInst #{{[0-9]+}} MOVF_I_MM
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
 # CHECK-EB: movz    $9, $6, $7        # encoding: [0x00,0xe6,0x48,0x58]
+# CHECK-EB-NEXT:                      # <MCInst #{{[0-9]+}} MOVZ_I_MM
 # CHECK-EB: movn    $9, $6, $7        # encoding: [0x00,0xe6,0x48,0x18]
+# CHECK-EB-NEXT:                      # <MCInst #{{[0-9]+}} MOVN_I_MM
 # CHECK-EB: movt    $9, $6, $fcc0     # encoding: [0x55,0x26,0x09,0x7b]
+# CHECK-EB-NEXT:                      # <MCInst #{{[0-9]+}} MOVT_I_MM
 # CHECK-EB: movf    $9, $6, $fcc0     # encoding: [0x55,0x26,0x01,0x7b]
+# CHECK-EB-NEXT:                      # <MCInst #{{[0-9]+}} MOVF_I_MM
      movz    $9, $6, $7
      movn    $9, $6, $7
      movt    $9, $6, $fcc0
      movf    $9, $6, $fcc0