[RFC][llvm-mca][patch 3/3] Add support for variant scheduling classes in llvm-mca.

[andreadb]

Summary

This patch is related to the LLVM-dev RFC "[RFC] MC support for variant scheduling classes".

As the title says, this patch teaches llvm-mca how to solve variant scheduling classes.

Note that this patch doesn't have a test case. I plan to add it soon.

[andreadb]

Patch updated. Note that this patch still needs a test case.

[andreadb]

Abandoning this patch in favor of D47374.

tools/llvm-mca/InstrBuilder.h

 /// descriptors (i.e. InstrDesc objects).
 /// Information from the machine scheduling model is used to identify processor
 /// resources that are consumed by an instruction.
 class InstrBuilder {
   const llvm::MCSubtargetInfo &STI;
   const llvm::MCInstrInfo &MCII;
   llvm::SmallVector<uint64_t, 8> ProcResourceMasks;
 
-  llvm::DenseMap<unsigned short, std::unique_ptr<const InstrDesc>> Descriptors;
+  llvm::DenseMap<const llvm::MCInst *, std::unique_ptr<const InstrDesc>>
+      Descriptors;
 
   const InstrDesc &createInstrDescImpl(const llvm::MCInst &MCI);
-
   InstrBuilder(const InstrBuilder &) = delete;
   InstrBuilder &operator=(const InstrBuilder &) = delete;
 
 public:
   InstrBuilder(const llvm::MCSubtargetInfo &sti, const llvm::MCInstrInfo &mcii)
       : STI(sti), MCII(mcii),
         ProcResourceMasks(STI.getSchedModel().getNumProcResourceKinds()) {
     computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks);

tools/llvm-mca/InstrBuilder.cpp

const InstrDesc &InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
 
   unsigned short Opcode = MCI.getOpcode();
   // Obtain the instruction descriptor from the opcode.
   const MCInstrDesc &MCDesc = MCII.get(Opcode);
   const MCSchedModel &SM = STI.getSchedModel();
 
   // Then obtain the scheduling class information from the instruction.
   unsigned SchedClassID = MCDesc.getSchedClass();
-  const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
+
+  // Try to solve variant scheduling classes.
+  while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())
+    SchedClassID =
+        STI.resolveVariantSchedClass(SchedClassID, &MCI, SM.getProcessorID());
+
+  const MCSchedClassDesc &SCDesc =
+      SchedClassID ? *SM.getSchedClassDesc(SchedClassID)
+                   : *SM.getSchedClassDesc(MCDesc.getSchedClass());
 
   // Create a new empty descriptor.
   std::unique_ptr<InstrDesc> ID = llvm::make_unique<InstrDesc>();
+  if (SCDesc.isVariant())
+    llvm::report_fatal_error(
+        "don't know how to resolve this variant scheduling class.\n");
 
-  if (SCDesc.isVariant()) {
-    WithColor::warning() << "don't know how to model variant opcodes.\n";
-    WithColor::note() << "assume 1 micro opcode.\n";
-    ID->NumMicroOps = 1U;
-  } else {
-    ID->NumMicroOps = SCDesc.NumMicroOps;
-  }
 
   if (MCDesc.isCall()) {
     // We don't correctly model calls.
     WithColor::warning() << "found a call in the input assembly sequence.\n";
     WithColor::note() << "call instructions are not correctly modeled. "
                       << "Assume a latency of 100cy.\n";
   }
 
const InstrDesc &InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
   computeMaxLatency(*ID, MCDesc, SCDesc, STI);
   populateWrites(*ID, MCI, MCDesc, SCDesc, STI);
   populateReads(*ID, MCI, MCDesc, SCDesc, STI);
 
   DEBUG(dbgs() << "\t\tMaxLatency=" << ID->MaxLatency << '\n');
   DEBUG(dbgs() << "\t\tNumMicroOps=" << ID->NumMicroOps << '\n');
 
   // Now add the new descriptor.
-  Descriptors[Opcode] = std::move(ID);
-  return *Descriptors[Opcode];
+  SchedClassID = MCDesc.getSchedClass();
+  Descriptors[&MCI] = std::move(ID);
+  return *Descriptors[&MCI];
 }
 
 const InstrDesc &InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) {
-  if (Descriptors.find_as(MCI.getOpcode()) == Descriptors.end())
+  if (Descriptors.find(&MCI) == Descriptors.end())
     return createInstrDescImpl(MCI);
-  return *Descriptors[MCI.getOpcode()];
+  return *Descriptors[&MCI];
 }
 
 std::unique_ptr<Instruction>
 InstrBuilder::createInstruction(const MCInst &MCI) {
   const InstrDesc &D = getOrCreateInstrDesc(MCI);
   std::unique_ptr<Instruction> NewIS = llvm::make_unique<Instruction>(D);
 
   // Initialize Reads first.

tools/llvm-mca/InstructionInfoView.cpp

void InstructionInfoView::printView(raw_ostream &OS) const {
   TempStream << "\n\nInstruction Info:\n";
   TempStream << "[1]: #uOps\n[2]: Latency\n[3]: RThroughput\n"
              << "[4]: MayLoad\n[5]: MayStore\n[6]: HasSideEffects\n\n";
 
   TempStream << "[1]    [2]    [3]    [4]    [5]    [6]\tInstructions:\n";
   for (unsigned I = 0, E = Instructions; I < E; ++I) {
     const MCInst &Inst = Source.getMCInstFromIndex(I);
     const MCInstrDesc &MCDesc = MCII.get(Inst.getOpcode());
+
+    // Obtain the scheduling class information from the instruction.
+    unsigned SchedClassID = MCDesc.getSchedClass();
+
+    // Try to solve variant scheduling classes.
+    while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())
+      SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &Inst,
+                                                  SM.getProcessorID());
+
     const MCSchedClassDesc &SCDesc =
-        *SM.getSchedClassDesc(MCDesc.getSchedClass());
+        SchedClassID ? *SM.getSchedClassDesc(SchedClassID)
+                     : *SM.getSchedClassDesc(MCDesc.getSchedClass());
 
     unsigned NumMicroOpcodes = SCDesc.NumMicroOps;
     unsigned Latency = MCSchedModel::computeInstrLatency(STI, SCDesc);
     Optional<double> RThroughput =
         MCSchedModel::getReciprocalThroughput(STI, SCDesc);
 
     TempStream << ' ' << NumMicroOpcodes << "    ";
     if (NumMicroOpcodes < 10)