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Differential D46689

[mips] Correct the predicates of indexed floating point stores and loads.
ClosedPublic

Authored by sdardis on May 10 2018, 4:41 AM.

Details

Reviewers
atanasyan
abeserminji
smaksimovic
Commits
rGfba036209680: [mips] Correct the predicates of indexed floating point stores and loads.
rL332227: [mips] Correct the predicates of indexed floating point stores and loads.
Summary

Also, fix the register class for microMIPS.

Diff Detail

Repository
rL LLVM

Event Timeline

sdardis created this revision.May 10 2018, 4:41 AM
Herald added subscribers: arichardson, dschuff. · View Herald TranscriptMay 10 2018, 4:41 AM
atanasyan accepted this revision.May 10 2018, 10:14 PM

LGTM

This revision is now accepted and ready to land.May 10 2018, 10:14 PM
Closed by commit rL332227: [mips] Correct the predicates of indexed floating point stores and loads. (authored by sdardis). · Explain WhyMay 14 2018, 3:56 AM
This revision was automatically updated to reflect the committed changes.
sdardis mentioned this in rL332241: [mips] Add missing test case from r332227.May 14 2018, 6:22 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
23 lines
5 lines
test/
MC/
Disassembler/
Mips/
micromips32r3/
2 lines
2 lines
Mips/
6 lines

Diff 146575

llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td

Show All 35 Linesdefm FADD : ADDS_MMM<"add.d", II_ADD_D, 1, fadd>,
ADDS_FM_MM<1, 0x30>, ISA_MICROMIPS; ADDS_FM_MM<1, 0x30>, ISA_MICROMIPS;
defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>, defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>,
ADDS_FM_MM<1, 0xf0>, ISA_MICROMIPS; ADDS_FM_MM<1, 0xf0>, ISA_MICROMIPS;
defm FMUL : ADDS_MMM<"mul.d", II_MUL_D, 1, fmul>, defm FMUL : ADDS_MMM<"mul.d", II_MUL_D, 1, fmul>,
ADDS_FM_MM<1, 0xb0>, ISA_MICROMIPS; ADDS_FM_MM<1, 0xb0>, ISA_MICROMIPS;
defm FSUB : ADDS_MMM<"sub.d", II_SUB_D, 0, fsub>, defm FSUB : ADDS_MMM<"sub.d", II_SUB_D, 0, fsub>,
ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS; ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS;
let isCodeGenOnly = 1 in { let DecoderNamespace = "MicroMips" in {
def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6; LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,
SWXC1_FM_MM<0x88>, ISA_MICROMIPS32_NOT_MIPS32R6; SWXC1_FM_MM<0x88>, ISA_MICROMIPS32_NOT_MIPS32R6;
// FIXME: These instruction definitions are incorrect. They should be 64-bit def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>,
// FPU only. LWXC1_FM_MM<0x148>, FGR_64, ISA_MICROMIPS32_NOT_MIPS32R6;
def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>,
LWXC1_FM_MM<0x148>, ISA_MICROMIPS32_NOT_MIPS32R6; SWXC1_FM_MM<0x188>, FGR_64, ISA_MICROMIPS32_NOT_MIPS32R6;
def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, }
SWXC1_FM_MM<0x188>, ISA_MICROMIPS32_NOT_MIPS32R6; let isCodeGenOnly = 1 in {
def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>,
CEQS_FM_MM<0>, ISA_MICROMIPS32_NOT_MIPS32R6 { CEQS_FM_MM<0>, ISA_MICROMIPS32_NOT_MIPS32R6 {
// FIXME: This is a required to work around the fact that these instructions // FIXME: This is a required to work around the fact that these instructions
// only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
// fcc register set is used directly. // fcc register set is used directly.
bits<3> fcc = 0; bits<3> fcc = 0;
} }
▲ Show 20 Lines • Show All 355 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsInstrFPU.td

Show First 20 Lines • Show All 570 Lines • ▼ Show 20 Lineslet DecoderNamespace="MipsFP64" in {
def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
} }
// Load/store doubleword indexed unaligned. // Load/store doubleword indexed unaligned.
// FIXME: This instruction should not be defined for FGR_32. // FIXME: This instruction should not be defined for FGR_32.
let AdditionalPredicates = [IsNotNaCl] in { let AdditionalPredicates = [IsNotNaCl, NotInMicroMips] in {
def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
} }
let DecoderNamespace="MipsFP64" in { let AdditionalPredicates = [IsNotNaCl, NotInMicroMips],
DecoderNamespace="MipsFP64" in {
def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
} }
/// Floating-point Aritmetic /// Floating-point Aritmetic
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
▲ Show 20 Lines • Show All 335 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt

Show All 13 Lines
0x02 0x54 0x7b 0x20 # CHECK: mov.d $f0, $f2 0x02 0x54 0x7b 0x20 # CHECK: mov.d $f0, $f2
0x02 0x54 0x7b 0x2b # CHECK: neg.d $f0, $f2 0x02 0x54 0x7b 0x2b # CHECK: neg.d $f0, $f2
0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2 0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2
0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2 0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2
0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2 0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2
0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2 0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2
0x82 0x54 0x3b 0x01 # CHECK: cvt.l.s $f4, $f2 0x82 0x54 0x3b 0x01 # CHECK: cvt.l.s $f4, $f2
0x82 0x54 0x3b 0x41 # CHECK: cvt.l.d $f4, $f2 0x82 0x54 0x3b 0x41 # CHECK: cvt.l.d $f4, $f2
0x85 0x54 0x48 0x21 # CHECK: luxc1 $f4, $4($5)
0x85 0x54 0x88 0x21 # CHECK: suxc1 $f4, $4($5)

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt

Show All 13 Lines
0x54 0x02 0x20 0x7b # CHECK: mov.d $f0, $f2 0x54 0x02 0x20 0x7b # CHECK: mov.d $f0, $f2
0x54 0x02 0x2b 0x7b # CHECK: neg.d $f0, $f2 0x54 0x02 0x2b 0x7b # CHECK: neg.d $f0, $f2
0x54 0x02 0x49 0x3b # CHECK: cvt.w.d $f0, $f2 0x54 0x02 0x49 0x3b # CHECK: cvt.w.d $f0, $f2
0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2 0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2
0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2 0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2
0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2 0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2
0x54 0x82 0x01 0x3b # CHECK: cvt.l.s $f4, $f2 0x54 0x82 0x01 0x3b # CHECK: cvt.l.s $f4, $f2
0x54 0x82 0x41 0x3b # CHECK: cvt.l.d $f4, $f2 0x54 0x82 0x41 0x3b # CHECK: cvt.l.d $f4, $f2
0x54 0x85 0x21 0x48 # CHECK: luxc1 $f4, $4($5)
0x54 0x85 0x21 0x88 # CHECK: suxc1 $f4, $4($5)

llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s

Show All 19 Lines
# CHECK-EL: lwc1 $f2, 4($6) # encoding: [0x46,0x9c,0x04,0x00] # CHECK-EL: lwc1 $f2, 4($6) # encoding: [0x46,0x9c,0x04,0x00]
# CHECK-EL: ldc1 $f2, 4($6) # encoding: [0x46,0xbc,0x04,0x00] # CHECK-EL: ldc1 $f2, 4($6) # encoding: [0x46,0xbc,0x04,0x00]
# CHECK-EL: swc1 $f2, 4($6) # encoding: [0x46,0x98,0x04,0x00] # CHECK-EL: swc1 $f2, 4($6) # encoding: [0x46,0x98,0x04,0x00]
# CHECK-EL: sdc1 $f2, 4($6) # encoding: [0x46,0xb8,0x04,0x00] # CHECK-EL: sdc1 $f2, 4($6) # encoding: [0x46,0xb8,0x04,0x00]
# CHECK-EL: bc1f 1332 # encoding: [0x80,0x43,0x9a,0x02] # CHECK-EL: bc1f 1332 # encoding: [0x80,0x43,0x9a,0x02]
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK-EL: bc1t 1332 # encoding: [0xa0,0x43,0x9a,0x02] # CHECK-EL: bc1t 1332 # encoding: [0xa0,0x43,0x9a,0x02]
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK-EL: luxc1 $f2, $4($6) # encoding: [0x86,0x54,0x48,0x11]
# CHECK-EL: suxc1 $f2, $4($6) # encoding: [0x86,0x54,0x88,0x11]
# CHECK-EL: ceil.w.s $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x1b] # CHECK-EL: ceil.w.s $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x1b]
# CHECK-EL: ceil.w.d $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x5b] # CHECK-EL: ceil.w.d $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x5b]
# CHECK-EL: cvt.w.s $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x09] # CHECK-EL: cvt.w.s $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x09]
# CHECK-EL: cvt.w.d $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x49] # CHECK-EL: cvt.w.d $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x49]
# CHECK-EL: floor.w.s $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x0b] # CHECK-EL: floor.w.s $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x0b]
# CHECK-EL: floor.w.d $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x4b] # CHECK-EL: floor.w.d $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x4b]
# CHECK-EL: round.w.s $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x3b] # CHECK-EL: round.w.s $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x3b]
# CHECK-EL: round.w.d $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x7b] # CHECK-EL: round.w.d $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x7b]
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
# CHECK-EB: lwc1 $f2, 4($6) # encoding: [0x9c,0x46,0x00,0x04] # CHECK-EB: lwc1 $f2, 4($6) # encoding: [0x9c,0x46,0x00,0x04]
# CHECK-EB: ldc1 $f2, 4($6) # encoding: [0xbc,0x46,0x00,0x04] # CHECK-EB: ldc1 $f2, 4($6) # encoding: [0xbc,0x46,0x00,0x04]
# CHECK-EB: swc1 $f2, 4($6) # encoding: [0x98,0x46,0x00,0x04] # CHECK-EB: swc1 $f2, 4($6) # encoding: [0x98,0x46,0x00,0x04]
# CHECK-EB: sdc1 $f2, 4($6) # encoding: [0xb8,0x46,0x00,0x04] # CHECK-EB: sdc1 $f2, 4($6) # encoding: [0xb8,0x46,0x00,0x04]
# CHECK-EB: bc1f 1332 # encoding: [0x43,0x80,0x02,0x9a] # CHECK-EB: bc1f 1332 # encoding: [0x43,0x80,0x02,0x9a]
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK-EB: bc1t 1332 # encoding: [0x43,0xa0,0x02,0x9a] # CHECK-EB: bc1t 1332 # encoding: [0x43,0xa0,0x02,0x9a]
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK-EB: luxc1 $f2, $4($6) # encoding: [0x54,0x86,0x11,0x48]
# CHECK-EB: suxc1 $f2, $4($6) # encoding: [0x54,0x86,0x11,0x88]
# CHECK-EB: ceil.w.s $f6, $f8 # encoding: [0x54,0xc8,0x1b,0x3b] # CHECK-EB: ceil.w.s $f6, $f8 # encoding: [0x54,0xc8,0x1b,0x3b]
# CHECK-EB: ceil.w.d $f6, $f8 # encoding: [0x54,0xc8,0x5b,0x3b] # CHECK-EB: ceil.w.d $f6, $f8 # encoding: [0x54,0xc8,0x5b,0x3b]
# CHECK-EB: cvt.w.s $f6, $f8 # encoding: [0x54,0xc8,0x09,0x3b] # CHECK-EB: cvt.w.s $f6, $f8 # encoding: [0x54,0xc8,0x09,0x3b]
# CHECK-EB: cvt.w.d $f6, $f8 # encoding: [0x54,0xc8,0x49,0x3b] # CHECK-EB: cvt.w.d $f6, $f8 # encoding: [0x54,0xc8,0x49,0x3b]
# CHECK-EB: floor.w.s $f6, $f8 # encoding: [0x54,0xc8,0x0b,0x3b] # CHECK-EB: floor.w.s $f6, $f8 # encoding: [0x54,0xc8,0x0b,0x3b]
# CHECK-EB: floor.w.d $f6, $f8 # encoding: [0x54,0xc8,0x4b,0x3b] # CHECK-EB: floor.w.d $f6, $f8 # encoding: [0x54,0xc8,0x4b,0x3b]
# CHECK-EB: round.w.s $f6, $f8 # encoding: [0x54,0xc8,0x3b,0x3b] # CHECK-EB: round.w.s $f6, $f8 # encoding: [0x54,0xc8,0x3b,0x3b]
# CHECK-EB: round.w.d $f6, $f8 # encoding: [0x54,0xc8,0x7b,0x3b] # CHECK-EB: round.w.d $f6, $f8 # encoding: [0x54,0xc8,0x7b,0x3b]
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines# CHECK-EB: nmsub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x2a]
sub.s $f4, $f6, $f8 sub.s $f4, $f6, $f8
sub.d $f4, $f6, $f8 sub.d $f4, $f6, $f8
lwc1 $f2, 4($6) lwc1 $f2, 4($6)
ldc1 $f2, 4($6) ldc1 $f2, 4($6)
swc1 $f2, 4($6) swc1 $f2, 4($6)
sdc1 $f2, 4($6) sdc1 $f2, 4($6)
bc1f 1332 bc1f 1332
bc1t 1332 bc1t 1332
luxc1 $f2, $4($6)
suxc1 $f2, $4($6)
ceil.w.s $f6, $f8 ceil.w.s $f6, $f8
ceil.w.d $f6, $f8 ceil.w.d $f6, $f8
cvt.w.s $f6, $f8 cvt.w.s $f6, $f8
cvt.w.d $f6, $f8 cvt.w.d $f6, $f8
floor.w.s $f6, $f8 floor.w.s $f6, $f8
floor.w.d $f6, $f8 floor.w.d $f6, $f8
round.w.s $f6, $f8 round.w.s $f6, $f8
round.w.d $f6, $f8 round.w.d $f6, $f8
Show All 36 Lines