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Differential D46390

[mips] Correct the predicates of cvt.fmt.fmt instructions
ClosedPublic

Authored by sdardis on May 3 2018, 7:19 AM.

Details

Reviewers
atanasyan
smaksimovic
abeserminji
Commits
rGce6ada41513e: [mips] Correct the predicates of cvt.fmt.fmt instructions
rL331969: [mips] Correct the predicates of cvt.fmt.fmt instructions

Diff Detail

Event Timeline

sdardis created this revision.May 3 2018, 7:19 AM
Herald added a subscriber: arichardson. · View Herald TranscriptMay 3 2018, 7:19 AM
atanasyan accepted this revision.May 4 2018, 12:10 AM

LGTM

This revision is now accepted and ready to land.May 4 2018, 12:10 AM
Closed by commit rL331969: [mips] Correct the predicates of cvt.fmt.fmt instructions (authored by sdardis). · Explain WhyMay 10 2018, 3:47 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
18 lines
29 lines
test/
MC/
Disassembler/
Mips/
micromips32r3/
2 lines
2 lines
Mips/
10 lines
micromips/
4 lines
mips3/
30 lines
mips4/
30 lines
mips5/
30 lines
mips64/
30 lines
mips64r2/
30 lines
mips64r3/
30 lines
mips64r5/
30 lines

Diff 145015

lib/Target/Mips/MicroMipsInstrFPU.td

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
} }
let DecoderNamespace = "MicroMips" in { let DecoderNamespace = "MicroMips" in {
def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>, def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,
BC1F_FM_MM<0x1c>, ISA_MICROMIPS32_NOT_MIPS32R6; BC1F_FM_MM<0x1c>, ISA_MICROMIPS32_NOT_MIPS32R6;
def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>, def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
BC1F_FM_MM<0x1d>, ISA_MICROMIPS32_NOT_MIPS32R6; BC1F_FM_MM<0x1d>, ISA_MICROMIPS32_NOT_MIPS32R6;
def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS;
} }
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS;
def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd,
II_ROUND>, ROUND_W_FM_MM<0, 0xec>, II_ROUND>, ROUND_W_FM_MM<0, 0xec>,
ISA_MICROMIPS; ISA_MICROMIPS;
def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>,
ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32; ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32;
def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>, def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>,
ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32; ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32;
def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd,
II_ROUND>, ROUND_W_FM_MM<1, 0xec>, II_ROUND>, ROUND_W_FM_MM<1, 0xec>,
ISA_MICROMIPS, FGR_32; ISA_MICROMIPS, FGR_32;
def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32; ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32;
}
let DecoderNamespace = "MicroMips" in {
def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64; ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64;
def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64; ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64;
}
let DecoderNamespace = "MicroMips" in {
def CVT_W_D32_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>, def CVT_W_D32_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32; ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32;
} }
let DecoderNamespace = "MicroMipsFP64" in { let DecoderNamespace = "MicroMipsFP64" in {
def CVT_W_D64_MM : ABSS_FT<"cvt.w.d", FGR32Opnd, FGR64Opnd, II_CVT>, def CVT_W_D64_MM : ABSS_FT<"cvt.w.d", FGR32Opnd, FGR64Opnd, II_CVT>,
ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_64; ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_64;
} }
Show All 37 Lines def CVT_D64_W_MM : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_64; ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_64;
def CVT_S_D64_MM : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, def CVT_S_D64_MM : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_64; ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_64;
} }
let DecoderNamespace = "MicroMips" in { let DecoderNamespace = "MicroMips" in {
def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32; ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32;
}
def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS; ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS;
}
defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>; defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>;
defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>; defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>;
let DecoderNamespace = "MicroMips" in { let DecoderNamespace = "MicroMips" in {
def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>, II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
▲ Show 20 Lines • Show All 243 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrFPU.td

Show First 20 Lines • Show All 352 Lines • ▼ Show 20 Linesdef ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
ABSS_FM<0xc, 16>, ISA_MIPS2; ABSS_FM<0xc, 16>, ISA_MIPS2;
defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2; defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
ABSS_FM<0xd, 16>, ISA_MIPS2; ABSS_FM<0xd, 16>, ISA_MIPS2;
def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
ABSS_FM<0xe, 16>, ISA_MIPS2; ABSS_FM<0xe, 16>, ISA_MIPS2;
def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
ABSS_FM<0xf, 16>, ISA_MIPS2; ABSS_FM<0xf, 16>, ISA_MIPS2;
let AdditionalPredicates = [NotInMicroMips] in
def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x24, 16>; ABSS_FM<0x24, 16>, ISA_MIPS1;
defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>, ISA_MIPS1;
} }
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>, def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2; ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>, def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>,
ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 { ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 {
let BaseOpcode = "RECIP_D32"; let BaseOpcode = "RECIP_D32";
Show All 29 Lines def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,
ABSS_FM<0xa, 17>, FGR_64; ABSS_FM<0xa, 17>, FGR_64;
def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>, def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,
ABSS_FM<0xb, 16>, FGR_64; ABSS_FM<0xb, 16>, FGR_64;
def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>, def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,
ABSS_FM<0xb, 17>, FGR_64; ABSS_FM<0xb, 17>, FGR_64;
} }
} }
def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x20, 20>;
let AdditionalPredicates = [NotInMicroMips] in{ let AdditionalPredicates = [NotInMicroMips] in{
def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x20, 20>, ISA_MIPS1;
def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x25, 16>, INSN_MIPS3_32R2; ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x25, 17>, INSN_MIPS3_32R2; ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
} }
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
ABSS_FM<0x20, 17>, FGR_32; ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_32;
def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 16>, FGR_32; ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_32;
def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 20>, FGR_32; ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32;
} }
let DecoderNamespace = "MipsFP64" in { let DecoderNamespace = "MipsFP64" in {
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 21>, FGR_64; ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64;
def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 17>, FGR_64; ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_64;
def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 20>, FGR_64; ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_64;
def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 16>, FGR_64; ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_64;
}
def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x21, 21>, FGR_64; ABSS_FM<0x21, 21>, INSN_MIPS3_32R2, FGR_64;
}
} }
let isPseudo = 1, isCodeGenOnly = 1 in { let isPseudo = 1, isCodeGenOnly = 1 in {
def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>; def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>; def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>; def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
▲ Show 20 Lines • Show All 476 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt

Show All 11 Lines
0x82 0x54 0xb0 0x01 # CHECK: mul.d $f0, $f2, $f4 0x82 0x54 0xb0 0x01 # CHECK: mul.d $f0, $f2, $f4
0x82 0x54 0xf0 0x01 # CHECK: div.d $f0, $f2, $f4 0x82 0x54 0xf0 0x01 # CHECK: div.d $f0, $f2, $f4
0x02 0x54 0x7b 0x20 # CHECK: mov.d $f0, $f2 0x02 0x54 0x7b 0x20 # CHECK: mov.d $f0, $f2
0x02 0x54 0x7b 0x2b # CHECK: neg.d $f0, $f2 0x02 0x54 0x7b 0x2b # CHECK: neg.d $f0, $f2
0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2 0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2
0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2 0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2
0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2 0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2
0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2 0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2
0x82 0x54 0x3b 0x01 # CHECK: cvt.l.s $f4, $f2
0x82 0x54 0x3b 0x41 # CHECK: cvt.l.d $f4, $f2

test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt

Show All 11 Lines
0x54 0x82 0x01 0xb0 # CHECK: mul.d $f0, $f2, $f4 0x54 0x82 0x01 0xb0 # CHECK: mul.d $f0, $f2, $f4
0x54 0x82 0x01 0xf0 # CHECK: div.d $f0, $f2, $f4 0x54 0x82 0x01 0xf0 # CHECK: div.d $f0, $f2, $f4
0x54 0x02 0x20 0x7b # CHECK: mov.d $f0, $f2 0x54 0x02 0x20 0x7b # CHECK: mov.d $f0, $f2
0x54 0x02 0x2b 0x7b # CHECK: neg.d $f0, $f2 0x54 0x02 0x2b 0x7b # CHECK: neg.d $f0, $f2
0x54 0x02 0x49 0x3b # CHECK: cvt.w.d $f0, $f2 0x54 0x02 0x49 0x3b # CHECK: cvt.w.d $f0, $f2
0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2 0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2
0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2 0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2
0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2 0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2
0x54 0x82 0x01 0x3b # CHECK: cvt.l.s $f4, $f2
0x54 0x82 0x41 0x3b # CHECK: cvt.l.d $f4, $f2

test/MC/Mips/micromips-fpu-instructions.s

Show All 40 Lines
# CHECK-EL: trunc.w.d $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x6b] # CHECK-EL: trunc.w.d $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x6b]
# CHECK-EL: abs.s $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x03] # CHECK-EL: abs.s $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x03]
# CHECK-EL: abs.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x23] # CHECK-EL: abs.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x23]
# CHECK-EL: mov.s $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x00] # CHECK-EL: mov.s $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x00]
# CHECK-EL: mov.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x20] # CHECK-EL: mov.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x20]
# CHECK-EL: neg.s $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x0b] # CHECK-EL: neg.s $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x0b]
# CHECK-EL: neg.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x2b] # CHECK-EL: neg.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x2b]
# CHECK-EL: cvt.d.s $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x13] # CHECK-EL: cvt.d.s $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x13]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S_MM
# CHECK-EL: cvt.d.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x33] # CHECK-EL: cvt.d.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x33]
# CHECK-EL: # <MCInst #{{.*}} CVT_D32_W_MM # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W_MM
# CHECK-EL: cvt.s.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x1b] # CHECK-EL: cvt.s.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x1b]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D32_MM
# CHECK-EL: cvt.s.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x3b] # CHECK-EL: cvt.s.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x3b]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CVT_S_W_MM
# CHECK-EL: cfc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x10] # CHECK-EL: cfc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x10]
# CHECK-EL: ctc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x18] # CHECK-EL: ctc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x18]
# CHECK-EL: mfc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x20] # CHECK-EL: mfc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x20]
# CHECK-EL: mtc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x28] # CHECK-EL: mtc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x28]
# CHECK-EL: mfhc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x30] # CHECK-EL: mfhc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x30]
# CHECK-EL: mthc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x38] # CHECK-EL: mthc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x38]
# CHECK-EL: movz.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x20] # CHECK-EL: movz.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x20]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_S_MM # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_S_MM
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# CHECK-EB: trunc.w.d $f6, $f8 # encoding: [0x54,0xc8,0x6b,0x3b] # CHECK-EB: trunc.w.d $f6, $f8 # encoding: [0x54,0xc8,0x6b,0x3b]
# CHECK-EB: abs.s $f6, $f8 # encoding: [0x54,0xc8,0x03,0x7b] # CHECK-EB: abs.s $f6, $f8 # encoding: [0x54,0xc8,0x03,0x7b]
# CHECK-EB: abs.d $f6, $f8 # encoding: [0x54,0xc8,0x23,0x7b] # CHECK-EB: abs.d $f6, $f8 # encoding: [0x54,0xc8,0x23,0x7b]
# CHECK-EB: mov.s $f6, $f8 # encoding: [0x54,0xc8,0x00,0x7b] # CHECK-EB: mov.s $f6, $f8 # encoding: [0x54,0xc8,0x00,0x7b]
# CHECK-EB: mov.d $f6, $f8 # encoding: [0x54,0xc8,0x20,0x7b] # CHECK-EB: mov.d $f6, $f8 # encoding: [0x54,0xc8,0x20,0x7b]
# CHECK-EB: neg.s $f6, $f8 # encoding: [0x54,0xc8,0x0b,0x7b] # CHECK-EB: neg.s $f6, $f8 # encoding: [0x54,0xc8,0x0b,0x7b]
# CHECK-EB: neg.d $f6, $f8 # encoding: [0x54,0xc8,0x2b,0x7b] # CHECK-EB: neg.d $f6, $f8 # encoding: [0x54,0xc8,0x2b,0x7b]
# CHECK-EB: cvt.d.s $f6, $f8 # encoding: [0x54,0xc8,0x13,0x7b] # CHECK-EB: cvt.d.s $f6, $f8 # encoding: [0x54,0xc8,0x13,0x7b]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S_MM
# CHECK-EB: cvt.d.w $f6, $f8 # encoding: [0x54,0xc8,0x33,0x7b] # CHECK-EB: cvt.d.w $f6, $f8 # encoding: [0x54,0xc8,0x33,0x7b]
# CHECK-EB: # <MCInst #{{.*}} CVT_D32_W_MM # CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W_MM
# CHECK-EB: cvt.s.d $f6, $f8 # encoding: [0x54,0xc8,0x1b,0x7b] # CHECK-EB: cvt.s.d $f6, $f8 # encoding: [0x54,0xc8,0x1b,0x7b]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D32_MM
# CHECK-EB: cvt.s.w $f6, $f8 # encoding: [0x54,0xc8,0x3b,0x7b] # CHECK-EB: cvt.s.w $f6, $f8 # encoding: [0x54,0xc8,0x3b,0x7b]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CVT_S_W_MM
# CHECK-EB: cfc1 $6, $0 # encoding: [0x54,0xc0,0x10,0x3b] # CHECK-EB: cfc1 $6, $0 # encoding: [0x54,0xc0,0x10,0x3b]
# CHECK-EB: ctc1 $6, $0 # encoding: [0x54,0xc0,0x18,0x3b] # CHECK-EB: ctc1 $6, $0 # encoding: [0x54,0xc0,0x18,0x3b]
# CHECK-EB: mfc1 $6, $f8 # encoding: [0x54,0xc8,0x20,0x3b] # CHECK-EB: mfc1 $6, $f8 # encoding: [0x54,0xc8,0x20,0x3b]
# CHECK-EB: mtc1 $6, $f8 # encoding: [0x54,0xc8,0x28,0x3b] # CHECK-EB: mtc1 $6, $f8 # encoding: [0x54,0xc8,0x28,0x3b]
# CHECK-EB: mfhc1 $6, $f8 # encoding: [0x54,0xc8,0x30,0x3b] # CHECK-EB: mfhc1 $6, $f8 # encoding: [0x54,0xc8,0x30,0x3b]
# CHECK-EB: mthc1 $6, $f8 # encoding: [0x54,0xc8,0x38,0x3b] # CHECK-EB: mthc1 $6, $f8 # encoding: [0x54,0xc8,0x38,0x3b]
# CHECK-EB: movz.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x78] # CHECK-EB: movz.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x78]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_S_MM # CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_S_MM
▲ Show 20 Lines • Show All 83 Lines • Show Last 20 Lines

test/MC/Mips/micromips/valid-fp64.s

Show All 9 Lines
cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x54,0x02,0x13,0x7b] cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x54,0x02,0x13,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_S_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_S_MM
cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x54,0x02,0x33,0x7b] cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x54,0x02,0x33,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_W_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_W_MM
cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x54,0x02,0x1b,0x7b] cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x54,0x02,0x1b,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D64_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D64_MM
cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x54,0x02,0x49,0x3b] cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x54,0x02,0x49,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D64_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D64_MM
cvt.l.s $f4, $f2 # CHECK: cvt.l.s $f4, $f2 # encoding: [0x54,0x82,0x01,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_L_S_MM
cvt.l.d $f4, $f2 # CHECK: cvt.l.d $f4, $f2 # encoding: [0x54,0x82,0x41,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_L_D64_MM
div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xf0] div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xf0]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D64_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D64_MM
mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x54,0x80,0x30,0x3b] mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x54,0x80,0x30,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D64_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D64_MM
mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x54,0x02,0x20,0x7b] mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x54,0x02,0x20,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D64_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D64_MM
mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x54,0x80,0x38,0x3b] mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x54,0x80,0x38,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D64_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D64_MM
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test/MC/Mips/mips3/valid.s

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Linesa:
c.sf.d $f30,$f0 c.sf.d $f30,$f0
c.sf.s $f14,$f22 c.sf.s $f14,$f22
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.l $f4,$f16 cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
cvt.d.s $f22,$f28 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
cvt.d.w $f26,$f11 cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
cvt.l.d $f24,$f15 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
cvt.l.s $f11,$f29 cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
cvt.s.d $f26,$f8 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.s.l $f15,$f30 cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
cvt.s.w $f22,$f15 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.w.d $f20,$f14 cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
cvt.w.s $f20,$f24 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
▲ Show 20 Lines • Show All 268 Lines • Show Last 20 Lines

test/MC/Mips/mips4/valid.s

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Linesa:
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.l $f4,$f16 cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
cvt.d.s $f22,$f28 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
cvt.d.w $f26,$f11 cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
cvt.l.d $f24,$f15 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
cvt.l.s $f11,$f29 cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
cvt.s.d $f26,$f8 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.s.l $f15,$f30 cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
cvt.s.w $f22,$f15 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.w.d $f20,$f14 cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
cvt.w.s $f20,$f24 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
▲ Show 20 Lines • Show All 297 Lines • Show Last 20 Lines

test/MC/Mips/mips5/valid.s

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Linesa:
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.l $f4,$f16 cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
cvt.d.s $f22,$f28 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
cvt.d.w $f26,$f11 cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
cvt.l.d $f24,$f15 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
cvt.l.s $f11,$f29 cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
cvt.s.d $f26,$f8 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.s.l $f15,$f30 cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
cvt.s.w $f22,$f15 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.w.d $f20,$f14 cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
cvt.w.s $f20,$f24 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
▲ Show 20 Lines • Show All 299 Lines • Show Last 20 Lines

test/MC/Mips/mips64/valid.s

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Linesa:
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.l $f4,$f16 cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
cvt.d.s $f22,$f28 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
cvt.d.w $f26,$f11 cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
cvt.l.d $f24,$f15 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
cvt.l.s $f11,$f29 cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
cvt.s.d $f26,$f8 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.s.l $f15,$f30 cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
cvt.s.w $f22,$f15 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.w.d $f20,$f14 cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
cvt.w.s $f20,$f24 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
▲ Show 20 Lines • Show All 315 Lines • Show Last 20 Lines

test/MC/Mips/mips64r2/valid.s

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Linesa:
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.l $f4,$f16 cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
cvt.d.s $f22,$f28 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
cvt.d.w $f26,$f11 cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
cvt.l.d $f24,$f15 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
cvt.l.s $f11,$f29 cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
cvt.s.d $f26,$f8 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.s.l $f15,$f30 cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
cvt.s.w $f22,$f15 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.w.d $f20,$f14 cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
cvt.w.s $f20,$f24 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
▲ Show 20 Lines • Show All 365 Lines • Show Last 20 Lines

test/MC/Mips/mips64r3/valid.s

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Linesa:
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.l $f4,$f16 cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
cvt.d.s $f22,$f28 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
cvt.d.w $f26,$f11 cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
cvt.l.d $f24,$f15 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
cvt.l.s $f11,$f29 cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
cvt.s.d $f26,$f8 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.s.l $f15,$f30 cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
cvt.s.w $f22,$f15 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.w.d $f20,$f14 cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
cvt.w.s $f20,$f24 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
▲ Show 20 Lines • Show All 354 Lines • Show Last 20 Lines

test/MC/Mips/mips64r5/valid.s

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Linesa:
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.l $f4,$f16 cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
cvt.d.s $f22,$f28 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
cvt.d.w $f26,$f11 cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
cvt.l.d $f24,$f15 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
cvt.l.s $f11,$f29 cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
cvt.s.d $f26,$f8 # CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.s.l $f15,$f30 cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
cvt.s.w $f22,$f15 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.w.d $f20,$f14 cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
cvt.w.s $f20,$f24 # CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
dadd $s3,$at,$ra dadd $s3,$at,$ra
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddi $sp,$s4,-27705 daddi $sp,$s4,-27705
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
daddiu $k0,$s6,-4586 daddiu $k0,$s6,-4586
daddu $s3,$at,$ra daddu $s3,$at,$ra
▲ Show 20 Lines • Show All 359 Lines • Show Last 20 Lines