[llvm-mca] Avoid exposing index values in the MCA interfaces.

[mattd]

Summary

This patch eliminates many places where we originally needed to pass index
values to represent an instruction. The index is still used as a key, in various parts of
MCA. I'm not comfortable eliminating the index just yet. By burying the index in
the instruction, we can avoid exposing that value in many places.

Eventually, we should consider removing the Instructions list in the Backend
all together, it's only used to hold and reclaim the memory for the allocated
Instruction instances. Instead we could pass around a smart pointer. But that's
a separate discussion/patch.

[mattd]

• Remove index values from the LSUnit routines. Essentially more of what this patch is trying to accomplish.

[andreadb]

Hi Matt,

what about passing an InstRef (i.e. a pair<index, Instruction>) to all those APIs?
I would not need to add a field to Instruction. The index is a SourceMgr concept. The only reason why those functionalities require it is mainly because they have to notify events, and events are based on the instruction index.

So, you could have that methods like checkRAT/checkXXX/etc. now accept an InstRef instead of a "index, Instruction" or (even worse) "index, InstrDesc". I would avout to change the Event classes if possible (at least for now).

About the instruction ownership issue you mentioned in your last paragraph: I am curious to see if it works the idea of having the RCU as the owner. An instruction exists if it is in-flight in the OoO backend. So, it must be known by the RCU through its entire lifetime. You could do some experiments to see if that idea works.

[mattd]

In D46367#1087554, @andreadb wrote:

Hi Matt,

what about passing an InstRef (i.e. a pair<index, Instruction>) to all those APIs?
I would not need to add a field to Instruction. The index is a SourceMgr concept. The only reason why those functionalities require it is mainly because they have to notify events, and events are based on the instruction index.

So, you could have that methods like checkRAT/checkXXX/etc. now accept an InstRef instead of a "index, Instruction" or (even worse) "index, InstrDesc". I would avout to change the Event classes if possible (at least for now).

Thanks for the feedback, and I see your point. Eventually, I'd like to eliminate the Index entirely. I suppose we could consider this change an intermediate step towards the goal. I was originally aiming at removing the Owner pointers in a few places. At least, for the cases where the Owner was only needed to perform an index-to-instruction lookup.

About the instruction ownership issue you mentioned in your last paragraph: I am curious to see if it works the idea of having the RCU as the owner. An instruction exists if it is in-flight in the OoO backend. So, it must be known by the RCU through its entire lifetime. You could do some experiments to see if that idea works.

I think that will work. Since the RCU will hold a reference to the Instruction, by design it would force the object to remain alive. Once the RCU finishes using the Instruction, then it will automatically be reclaimed.

[mattd]

Respin of the previous patch:

• InstRef is now a pair <SourceMgr index, Instruction *>, with added sanity checks and convenience accessors.
• SourceRef is a new type and defined as a pair <SourceMgr index, MCInst>

I'm not sure this is ideal, yet, but it is one step closer to sharing a common interface across various MCA components. The previous patch already updated the Event interface. I kept those changes, as it eliminates the need to have an Owner pointer for lookup in those cases, since we now have the InstRef containing the Instruction that was needed.

[andreadb]

Hi Matt,

This diff has not been taken against top of trunk. Could you please rebase the patch and then create a correct diff?
For example, class Instuction never had a field named SourceIndex!

Also, see my inline comments.

Thanks,
Andrea

tools/llvm-mca/Dispatch.cpp

329 ↗

(On Diff #145393)

Use an instruction reference here.
Instruction &IS = *IR.getInstruction();

tools/llvm-mca/InstrBuilder.cpp

429–431 ↗

(On Diff #145393)

Same. You should rebase against ToT.

tools/llvm-mca/InstrBuilder.h

62 ↗

(On Diff #145393)

Please correctly rebase this patch. This change should not have been here.

tools/llvm-mca/Instruction.h

20 ↗

(On Diff #145393)

Please remove this. See my comment below.
Essentially, raw_ostream is only used for debugging purposes here. Move the printing functionality to the cpp file, and guard the declaration of the printing functionality using a check on NDEBUG. This include can then be removed.

41 ↗

(On Diff #145393)

What's the advantage in having this constructor? I think you can remove it.
All the instruction references should be constructed using the other constructor at line 42.

48 ↗

(On Diff #145393)

Not needed. It is okay to return nullptr.

53 ↗

(On Diff #145393)

Not needed.

60–68 ↗

(On Diff #145393)

This code should be guarded against NDEBUG.
Everywhere else in the codebase we use method dump() to do debug prints. You should do the same, and move the definition in Instruction.cpp.

tools/llvm-mca/RetireControlUnit.cpp

31 ↗

(On Diff #145393)

Why a pointer? I think InstRef should always be passed by reference or by copy.
This diff doesn't match Upstream! The signature should have been different. reserveSlot accepts an instruction index, and not an instruction reference!

40 ↗

(On Diff #145393)

This is wrong.

57 ↗

(On Diff #145393)

Can this ever happen?

tools/llvm-mca/RetireControlUnit.h

50 ↗

(On Diff #145393)

It was an unsigned integer before. Now it is an InstRef. Please explain why?

77 ↗

(On Diff #145393)

This is incorrect. Regardless of the wrong diff.

tools/llvm-mca/Scheduler.cpp

412–413 ↗

(On Diff #145393)

const InstrDesc &D = Entry.second->getDesc();

[mattd]

Thanks for the review. Sorry for building on the previous patch, I should have rebased against ToT.

tools/llvm-mca/InstrBuilder.h

62 ↗

(On Diff #145393)

Sorry about that, I was just playing off of the previous patch for this that I was working on.

tools/llvm-mca/Instruction.h

41 ↗

(On Diff #145393)

I was allowing for the case of storing of InstRef objects in a container, not by reference or pointer. This would only be for the RCU's queue. But perhaps we remove this default ctor, and just store an Instruction pointer in the RUToken. I've discussed this more in a comment below.

48 ↗

(On Diff #145393)

Ok, I'll remove it. I was trying to detect any states that should not arise, but I wanted to guarantee that they did not occur. If, for instance, an InstRef was constructed with a nullptr value for the Instruction. Or some default construction never getting populated. But, as I mentioned in a comment above, and as you suggested, we can get rid of the default ctor. But that is somewhat dependent on how we define the RUToken, which is discussed in a different comment below.

60–68 ↗

(On Diff #145393)

I agree with the NDEBUG.

This overload is just providing a convenient way to pass an InstRef to an output stream. We were already passing index values to our debug output. Since we are now passing around InstRef in most places, I figured it would be nice to overload the output operator for InstRef, so that our existing debug prints would not have to call "getSourceIndex."

tools/llvm-mca/RetireControlUnit.cpp

31 ↗

(On Diff #145393)

Did you want to keep the original definition of reserveSlot, by taking an index? Since we are simplifying the interface where most routines take an InstRef, I think passing a reference would make sense, as it is later used for event notification. I was hoping to remove all of the Owner->getInstruction() lookups.

57 ↗

(On Diff #145393)

I'm not sure, so I figured it was a reasonable assertion to make.

tools/llvm-mca/RetireControlUnit.h

50 ↗

(On Diff #145393)

The reason is that the token is eventually used to signal that a particular instruction has retired, the call to notifyInstructionRetired in RetireControlUnit::cycleEvent. I was trying to avoid storing an index, since the notification mechanism would have to eventually perform a lookup of that index to get the instruction pointer. I was trying to decouple eventing from the component containing all of the instruction instances, I do realize that RCU will probably manage ownership of all Instructions at some point. I was trying to avoid having one component query another MCA component to get an instruction. We already have the instruction when we generate the RUToken values, so my thought was just to pass that information instead.

77 ↗

(On Diff #145393)

I agree, it shouldn't be a pointer. I'm not sure why I changed that, other than it was how things fell out from the previous patch. Sorry. I'll fix that.

[andreadb]

Thanks Matt,

tools/llvm-mca/InstrBuilder.h

62 ↗

(On Diff #145393)

No problem. It happens :-)

tools/llvm-mca/Instruction.h

60–68 ↗

(On Diff #145393)

Makes sense. Thanks.

tools/llvm-mca/RetireControlUnit.cpp

31 ↗

(On Diff #145393)

That’s okay. I was just confused by the presence of a pointer.

tools/llvm-mca/RetireControlUnit.h

50 ↗

(On Diff #145393)

Thanks for the explanation. Makes sense :-).

[mattd]

Updated this patch per some of the comments discussed:

• Rebased against the ToT.
• Added an NDEBUG guard to the debug output routine. I wanted to keep this routine to eliminate calls to getSourceIndex in our debug output. This allows us to keep the syntax in debug output code clean.
• Made a pointer a const ref for the formal parameter in RCU's reserveSlot(). I'm not sure why it was treated as a pointer previously. I have a feeling my earlier version of this patch was tossing around a Instruction * in that case, and I never adjusted for that.
• I wanted to remove the copy of the InstRef in the RUToken queue. That queue is a std::vector which we resize. This container requires a default InstRef ctor.

These changes allow us to partially decouple the RCU and Backend, in other words I've removed the Backend's "getInstruction" function. Only one eventing routine is still coupled to an index value, which couples the RCU and backend, eraseInstruction. However, in the future we will make the RCU the owner of instructions, so that coupling between components will disappear, as the RCU will be responsible for eraseInstrcuction.

[mattd]

Clean up the in the lambda in Scheduler::select by joining the queries for an instruction and its description.

[andreadb]

A few minor nits. Otherwise LGTM.

Thanks!

tools/llvm-mca/HWEventListener.h

52 ↗

(On Diff #145424)

Can you use a different name for the InstRef argument and the class field. Using the same name for both makes me feel a bit uncomfortable.

tools/llvm-mca/Instruction.h

20 ↗

(On Diff #145424)

I still think you should remove this include. It is only there because of method print, which should be also guarded against NDEBUG.

52 ↗

(On Diff #145424)

I think this should be guarded against NDEBUG.

tools/llvm-mca/LSUnit.h

19 ↗

(On Diff #145424)

I think you can just forward declare InstRef inside namespace mca. You probably don't need to include the entire "Instruction.h". Uses of InstRef are all in the cpp file (that file includes already Instruction.h).

[mattd]

• Instruction.h: NDEBUG guarded the InstRef::print()
• HWEventListener.h: Renamed a formal so that it is does not have the same name as a member variable.
• LSUnit.h: Forward decl 'class InstRef' and remove the inclusion of Instruction.h

[mattd]

Thanks for the review!

tools/llvm-mca/Instruction.h

20 ↗

(On Diff #145424)

I get build errors regarding raw_stream if the header is not there for debug builds, so I think it needs to stay, at least to support the overloaded output operator. I could guard the include directive; however, I don't see anywhere in the compiler that specifically guards against that header.

llvm/trunk/tools/llvm-mca/Backend.h

Backend(const llvm::MCSubtargetInfo &Subtarget,
     HWS->setDispatchUnit(DU.get());
   }
 
   void run() {
     while (SM.hasNext() || !DU->isRCUEmpty())
       runCycle(Cycles++);
   }
 
-  const Instruction &getInstruction(unsigned Index) const {
-    const auto It = Instructions.find(Index);
-    assert(It != Instructions.end() && "no running instructions with index");
-    assert(It->second);
-    return *It->second;
+  void eraseInstruction(const InstRef &IR) {
+    Instructions.erase(IR.getSourceIndex());
   }
-  void eraseInstruction(unsigned Index) { Instructions.erase(Index); }
 
   void addEventListener(HWEventListener *Listener);
   void notifyCycleBegin(unsigned Cycle);
   void notifyInstructionEvent(const HWInstructionEvent &Event);
   void notifyStallEvent(const HWStallEvent &Event);
   void notifyResourceAvailable(const ResourceRef &RR);
   void notifyReservedBuffers(llvm::ArrayRef<unsigned> Buffers);
   void notifyReleasedBuffers(llvm::ArrayRef<unsigned> Buffers);
   void notifyCycleEnd(unsigned Cycle);
 };
 } // namespace mca
 
 #endif

llvm/trunk/tools/llvm-mca/Backend.cpp

void Backend::addEventListener(HWEventListener *Listener) {
   if (Listener)
     Listeners.insert(Listener);
 }
 
 void Backend::runCycle(unsigned Cycle) {
   notifyCycleBegin(Cycle);
 
   while (SM.hasNext()) {
-    InstRef IR = SM.peekNext();
-    std::unique_ptr<Instruction> NewIS = IB.createInstruction(*IR.second);
+    SourceRef SR = SM.peekNext();
+    std::unique_ptr<Instruction> NewIS = IB.createInstruction(*SR.second);
     const InstrDesc &Desc = NewIS->getDesc();
-    if (!DU->isAvailable(Desc.NumMicroOps) ||
-        !DU->canDispatch(IR.first, *NewIS))
-      break;
-
     Instruction *IS = NewIS.get();
-    Instructions[IR.first] = std::move(NewIS);
-    DU->dispatch(IR.first, IS, STI);
+    InstRef IR(SR.first, IS);
+    if (!DU->isAvailable(Desc.NumMicroOps) || !DU->canDispatch(IR))
+      break;
+    Instructions[SR.first] = std::move(NewIS);
+    DU->dispatch(IR, STI);
     SM.updateNext();
   }
 
   notifyCycleEnd(Cycle);
 }
 
 void Backend::notifyCycleBegin(unsigned Cycle) {
   DEBUG(dbgs() << "[E] Cycle begin: " << Cycle << '\n');

llvm/trunk/tools/llvm-mca/Dispatch.h

class DispatchUnit {
   unsigned AvailableEntries;
   unsigned CarryOver;
   Scheduler *SC;
 
   std::unique_ptr<RegisterFile> RAT;
   std::unique_ptr<RetireControlUnit> RCU;
   Backend *Owner;
 
-  bool checkRAT(unsigned Index, const Instruction &Inst);
-  bool checkRCU(unsigned Index, const InstrDesc &Desc);
-  bool checkScheduler(unsigned Index, const InstrDesc &Desc);
+  bool checkRAT(const InstRef &IR);
+  bool checkRCU(const InstRef &IR);
+  bool checkScheduler(const InstRef &IR);
 
   void updateRAWDependencies(ReadState &RS, const llvm::MCSubtargetInfo &STI);
-  void notifyInstructionDispatched(unsigned IID,
+  void notifyInstructionDispatched(const InstRef &IR,
                                    llvm::ArrayRef<unsigned> UsedPhysRegs);
 
 public:
   DispatchUnit(Backend *B, const llvm::MCSchedModel &SM,
                const llvm::MCRegisterInfo &MRI, unsigned RegisterFileSize,
                unsigned MaxDispatchWidth, Scheduler *Sched)
       : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
         CarryOver(0U), SC(Sched),
         RAT(llvm::make_unique<RegisterFile>(SM, MRI, RegisterFileSize)),
         RCU(llvm::make_unique<RetireControlUnit>(SM, this)), Owner(B) {}
 
   unsigned getDispatchWidth() const { return DispatchWidth; }
 
   bool isAvailable(unsigned NumEntries) const {
     return NumEntries <= AvailableEntries || AvailableEntries == DispatchWidth;
   }
 
   bool isRCUEmpty() const { return RCU->isEmpty(); }
 
-  bool canDispatch(unsigned Index, const Instruction &Inst) {
-    const InstrDesc &Desc = Inst.getDesc();
-    assert(isAvailable(Desc.NumMicroOps));
-    return checkRCU(Index, Desc) && checkRAT(Index, Inst) &&
-           checkScheduler(Index, Desc);
+  bool canDispatch(const InstRef &IR) {
+    assert(isAvailable(IR.getInstruction()->getDesc().NumMicroOps));
+    return checkRCU(IR) && checkRAT(IR) && checkScheduler(IR);
   }
 
-  void dispatch(unsigned IID, Instruction *I, const llvm::MCSubtargetInfo &STI);
+  void dispatch(InstRef IR, const llvm::MCSubtargetInfo &STI);
 
   void collectWrites(llvm::SmallVectorImpl<WriteState *> &Vec,
                      unsigned RegID) const {
     return RAT->collectWrites(Vec, RegID);
   }
 
   void cycleEvent() {
     RCU->cycleEvent();
     AvailableEntries =
         CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
     CarryOver = CarryOver >= DispatchWidth ? CarryOver - DispatchWidth : 0U;
   }
 
-  void notifyInstructionRetired(unsigned Index);
+  void notifyInstructionRetired(const InstRef &IR);
 
-  void notifyDispatchStall(unsigned Index, unsigned EventType);
+  void notifyDispatchStall(const InstRef &IR, unsigned EventType);
 
   void onInstructionExecuted(unsigned TokenID) {
     RCU->onInstructionExecuted(TokenID);
   }
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 } // namespace mca
 
 #endif

llvm/trunk/tools/llvm-mca/Dispatch.cpp

for (unsigned I = 0, E = getNumRegisterFiles(); I < E; ++I) {
     dbgs() << "Register File #" << I;
     const RegisterMappingTracker &RMT = RegisterFiles[I];
     dbgs() << "\n  TotalMappings:        " << RMT.TotalMappings
            << "\n  NumUsedMappings:      " << RMT.NumUsedMappings << '\n';
   }
 }
 #endif
 
-void DispatchUnit::notifyInstructionDispatched(unsigned Index,
+void DispatchUnit::notifyInstructionDispatched(const InstRef &IR,
                                                ArrayRef<unsigned> UsedRegs) {
-  DEBUG(dbgs() << "[E] Instruction Dispatched: " << Index << '\n');
-  Owner->notifyInstructionEvent(HWInstructionDispatchedEvent(Index, UsedRegs));
+  DEBUG(dbgs() << "[E] Instruction Dispatched: " << IR << '\n');
+  Owner->notifyInstructionEvent(HWInstructionDispatchedEvent(IR, UsedRegs));
 }
 
-void DispatchUnit::notifyInstructionRetired(unsigned Index) {
-  DEBUG(dbgs() << "[E] Instruction Retired: " << Index << '\n');
-  const Instruction &IS = Owner->getInstruction(Index);
+void DispatchUnit::notifyInstructionRetired(const InstRef &IR) {
+  DEBUG(dbgs() << "[E] Instruction Retired: " << IR << '\n');
   SmallVector<unsigned, 4> FreedRegs(RAT->getNumRegisterFiles());
-  for (const std::unique_ptr<WriteState> &WS : IS.getDefs())
+  for (const std::unique_ptr<WriteState> &WS : IR.getInstruction()->getDefs())
     RAT->invalidateRegisterMapping(*WS.get(), FreedRegs);
-
-  Owner->notifyInstructionEvent(HWInstructionRetiredEvent(Index, FreedRegs));
-  Owner->eraseInstruction(Index);
+  Owner->notifyInstructionEvent(HWInstructionRetiredEvent(IR, FreedRegs));
+  Owner->eraseInstruction(IR);
 }
 
-bool DispatchUnit::checkRAT(unsigned Index, const Instruction &Instr) {
+bool DispatchUnit::checkRAT(const InstRef &IR) {
   SmallVector<unsigned, 4> RegDefs;
-  for (const std::unique_ptr<WriteState> &RegDef : Instr.getDefs())
+  for (const std::unique_ptr<WriteState> &RegDef :
+       IR.getInstruction()->getDefs())
     RegDefs.emplace_back(RegDef->getRegisterID());
 
   unsigned RegisterMask = RAT->isAvailable(RegDefs);
   // A mask with all zeroes means: register files are available.
   if (RegisterMask) {
-    Owner->notifyStallEvent(
-        HWStallEvent(HWStallEvent::RegisterFileStall, Index));
+    Owner->notifyStallEvent(HWStallEvent(HWStallEvent::RegisterFileStall, IR));
     return false;
   }
 
   return true;
 }
 
-bool DispatchUnit::checkRCU(unsigned Index, const InstrDesc &Desc) {
-  unsigned NumMicroOps = Desc.NumMicroOps;
+bool DispatchUnit::checkRCU(const InstRef &IR) {
+  const unsigned NumMicroOps = IR.getInstruction()->getDesc().NumMicroOps;
   if (RCU->isAvailable(NumMicroOps))
     return true;
   Owner->notifyStallEvent(
-      HWStallEvent(HWStallEvent::RetireControlUnitStall, Index));
+      HWStallEvent(HWStallEvent::RetireControlUnitStall, IR));
   return false;
 }
 
-bool DispatchUnit::checkScheduler(unsigned Index, const InstrDesc &Desc) {
-  return SC->canBeDispatched(Index, Desc);
+bool DispatchUnit::checkScheduler(const InstRef &IR) {
+  return SC->canBeDispatched(IR);
 }
 
 void DispatchUnit::updateRAWDependencies(ReadState &RS,
                                          const MCSubtargetInfo &STI) {
   SmallVector<WriteState *, 4> DependentWrites;
 
   collectWrites(DependentWrites, RS.getRegisterID());
   RS.setDependentWrites(DependentWrites.size());
for (WriteState *WS : DependentWrites) {
     unsigned WriteResID = WS->getWriteResourceID();
     int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
     WS->addUser(&RS, ReadAdvance);
   }
   // Prepare the set for another round.
   DependentWrites.clear();
 }
 
-void DispatchUnit::dispatch(unsigned IID, Instruction *NewInst,
-                            const MCSubtargetInfo &STI) {
+void DispatchUnit::dispatch(InstRef IR, const MCSubtargetInfo &STI) {
   assert(!CarryOver && "Cannot dispatch another instruction!");
-  unsigned NumMicroOps = NewInst->getDesc().NumMicroOps;
+  Instruction &IS = *IR.getInstruction();
+  const InstrDesc &Desc = IS.getDesc();
+  const unsigned NumMicroOps = Desc.NumMicroOps;
   if (NumMicroOps > DispatchWidth) {
     assert(AvailableEntries == DispatchWidth);
     AvailableEntries = 0;
     CarryOver = NumMicroOps - DispatchWidth;
   } else {
     assert(AvailableEntries >= NumMicroOps);
     AvailableEntries -= NumMicroOps;
   }
 
   // Update RAW dependencies if this instruction is not a zero-latency
   // instruction. The assumption is that a zero-latency instruction doesn't
   // require to be issued to the scheduler for execution. More importantly, it
   // doesn't have to wait on the register input operands.
-  const InstrDesc &Desc = NewInst->getDesc();
   if (Desc.MaxLatency || !Desc.Resources.empty())
-    for (std::unique_ptr<ReadState> &RS : NewInst->getUses())
+    for (std::unique_ptr<ReadState> &RS : IS.getUses())
       updateRAWDependencies(*RS, STI);
 
   // Allocate new mappings.
   SmallVector<unsigned, 4> RegisterFiles(RAT->getNumRegisterFiles());
-  for (std::unique_ptr<WriteState> &WS : NewInst->getDefs())
+  for (std::unique_ptr<WriteState> &WS : IS.getDefs())
     RAT->addRegisterMapping(*WS, RegisterFiles);
 
   // Reserve slots in the RCU, and notify the instruction that it has been
   // dispatched to the schedulers for execution.
-  NewInst->dispatch(RCU->reserveSlot(IID, NumMicroOps));
+  IS.dispatch(RCU->reserveSlot(IR, NumMicroOps));
 
   // Notify listeners of the "instruction dispatched" event.
-  notifyInstructionDispatched(IID, RegisterFiles);
+  notifyInstructionDispatched(IR, RegisterFiles);
 
   // Now move the instruction into the scheduler's queue.
   // The scheduler is responsible for checking if this is a zero-latency
   // instruction that doesn't consume pipeline/scheduler resources.
-  SC->scheduleInstruction(IID, *NewInst);
+  SC->scheduleInstruction(IR);
 }
 
 #ifndef NDEBUG
 void DispatchUnit::dump() const {
   RAT->dump();
   RCU->dump();
 }
 #endif
 } // namespace mca

llvm/trunk/tools/llvm-mca/HWEventListener.h

-
 //===----------------------- HWEventListener.h ------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the main interface for hardware event listeners.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_HWEVENTLISTENER_H
 #define LLVM_TOOLS_LLVM_MCA_HWEVENTLISTENER_H
 
+#include "Instruction.h"
 #include "llvm/ADT/ArrayRef.h"
 #include <utility>
 
 namespace mca {
 
 // An HWInstructionEvent represents state changes of instructions that
 // listeners might be interested in. Listeners can choose to ignore any event
 // they are not interested in.
enum GenericEventType {
     Issued,
     Executed,
     // Events generated by the Dispatch logic.
     Dispatched,
 
     LastGenericEventType,
   };
 
-  HWInstructionEvent(unsigned type, unsigned index)
-      : Type(type), Index(index) {}
+  HWInstructionEvent(unsigned type, const InstRef &Inst)
+      : Type(type), IR(Inst) {}
 
   // The event type. The exact meaning depends on the subtarget.
   const unsigned Type;
-  // The index of the instruction in the source manager.
-  const unsigned Index;
+
+  // The instruction this event was generated for.
+  const InstRef &IR;
 };
 
 class HWInstructionIssuedEvent : public HWInstructionEvent {
 public:
   using ResourceRef = std::pair<uint64_t, uint64_t>;
-  HWInstructionIssuedEvent(unsigned Index,
+  HWInstructionIssuedEvent(const InstRef &IR,
                            llvm::ArrayRef<std::pair<ResourceRef, double>> UR)
-      : HWInstructionEvent(HWInstructionEvent::Issued, Index),
-        UsedResources(UR) {}
+      : HWInstructionEvent(HWInstructionEvent::Issued, IR), UsedResources(UR) {}
 
   llvm::ArrayRef<std::pair<ResourceRef, double>> UsedResources;
 };
 
 class HWInstructionDispatchedEvent : public HWInstructionEvent {
 public:
-  HWInstructionDispatchedEvent(unsigned Index, llvm::ArrayRef<unsigned> Regs)
-      : HWInstructionEvent(HWInstructionEvent::Dispatched, Index),
+  HWInstructionDispatchedEvent(const InstRef &IR, llvm::ArrayRef<unsigned> Regs)
+      : HWInstructionEvent(HWInstructionEvent::Dispatched, IR),
         UsedPhysRegs(Regs) {}
   // Number of physical register allocated for this instruction. There is one
   // entry per register file.
   llvm::ArrayRef<unsigned> UsedPhysRegs;
 };
 
 class HWInstructionRetiredEvent : public HWInstructionEvent {
 public:
-  HWInstructionRetiredEvent(unsigned Index, llvm::ArrayRef<unsigned> Regs)
-      : HWInstructionEvent(HWInstructionEvent::Retired, Index),
+  HWInstructionRetiredEvent(const InstRef &IR, llvm::ArrayRef<unsigned> Regs)
+      : HWInstructionEvent(HWInstructionEvent::Retired, IR),
         FreedPhysRegs(Regs) {}
   // Number of register writes that have been architecturally committed. There
   // is one entry per register file.
   llvm::ArrayRef<unsigned> FreedPhysRegs;
 };
 
 // A HWStallEvent represents a pipeline stall caused by the lack of hardware
 // resources.
 class HWStallEvent {
 public:
   enum GenericEventType {
     Invalid = 0,
     // Generic stall events generated by the DispatchUnit.
     RegisterFileStall,
     RetireControlUnitStall,
     // Generic stall events generated by the Scheduler.
     DispatchGroupStall,
     SchedulerQueueFull,
     LoadQueueFull,
     StoreQueueFull,
     LastGenericEvent
   };
 
-  HWStallEvent(unsigned type, unsigned index) : Type(type), Index(index) {}
+  HWStallEvent(unsigned type, const InstRef &Inst) : Type(type), IR(Inst) {}
 
   // The exact meaning of the stall event type depends on the subtarget.
   const unsigned Type;
-  // The index of the instruction in the source manager.
-  const unsigned Index;
+
+  // The instruction this event was generated for.
+  const InstRef &IR;
 };
 
 class HWEventListener {
 public:
   // Generic events generated by the backend pipeline.
   virtual void onCycleBegin() {}
   virtual void onCycleEnd() {}
 

llvm/trunk/tools/llvm-mca/Instruction.h

 /// register writes and instructions.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_INSTRUCTION_H
 #define LLVM_TOOLS_LLVM_MCA_INSTRUCTION_H
 
 #include "llvm/Support/MathExtras.h"
+#include "llvm/Support/raw_ostream.h"
 #include <memory>
 #include <set>
 #include <vector>
 
 namespace mca {
 
 struct WriteDescriptor;
 struct ReadDescriptor;
 class WriteState;
 class ReadState;
 
 constexpr int UNKNOWN_CYCLES = -512;
 
+class Instruction;
+
+/// An InstRef contains both a SourceMgr index and Instruction pair.  The index
+/// is used as a unique identifier for the instruction.  MCA will make use of
+/// this index as a key throughout MCA.
+class InstRef : public std::pair<unsigned, Instruction *> {
+public:
+  InstRef() : std::pair<unsigned, Instruction *>(0, nullptr) {}
+  InstRef(unsigned Index, Instruction *I)
+      : std::pair<unsigned, Instruction *>(Index, I) {}
+
+  unsigned getSourceIndex() const { return first; }
+  Instruction *getInstruction() { return second; }
+  const Instruction *getInstruction() const { return second; }
+
+  /// Returns true if  this InstRef has been populated.
+  bool isValid() const { return second != nullptr; }
+
+#ifndef NDEBUG
+  void print(llvm::raw_ostream &OS) const { OS << getSourceIndex(); }
+#endif
+};
+
+#ifndef NDEBUG
+inline llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, const InstRef &IR) {
+  IR.print(OS);
+  return OS;
+}
+#endif
+
 /// A register write descriptor.
 struct WriteDescriptor {
   // Operand index. -1 if this is an implicit write.
   int OpIndex;
   // Write latency. Number of cycles before write-back stage.
   int Latency;
   // This field is set to a value different than zero only if this
   // is an implicit definition.

llvm/trunk/tools/llvm-mca/InstructionTables.cpp

 
 void InstructionTables::run() {
   ArrayRef<uint64_t> Masks = IB.getProcResourceMasks();
   SmallVector<std::pair<ResourceRef, double>, 4> UsedResources;
 
   // Create an instruction descriptor for every instruction in the sequence.
   while (S.hasNext()) {
     UsedResources.clear();
-    InstRef IR = S.peekNext();
-    std::unique_ptr<Instruction> Inst = IB.createInstruction(*IR.second);
+    SourceRef SR = S.peekNext();
+    std::unique_ptr<Instruction> Inst = IB.createInstruction(*SR.second);
     const InstrDesc &Desc = Inst->getDesc();
     // Now identify the resources consumed by this instruction.
     for (const std::pair<uint64_t, ResourceUsage> Resource : Desc.Resources) {
       // Skip zero-cycle resources (i.e. unused resources).
       if (!Resource.second.size())
         continue;
       double Cycles = static_cast<double>(Resource.second.size());
       unsigned Index =
for (const std::pair<uint64_t, ResourceUsage> Resource : Desc.Resources) {
         for (unsigned I2 = 0, E2 = SubUnit.NumUnits; I2 < E2; ++I2) {
           ResourceRef ResourceUnit = std::make_pair(SubUnitIdx, 1U << I2);
           UsedResources.emplace_back(std::make_pair(ResourceUnit, RUCycles));
         }
       }
     }
 
     // Now send a fake instruction issued event to all the views.
-    HWInstructionIssuedEvent Event(IR.first, UsedResources);
+    InstRef IR(SR.first, Inst.get());
+    HWInstructionIssuedEvent Event(IR, UsedResources);
     for (std::unique_ptr<View> &Listener : Views)
       Listener->onInstructionEvent(Event);
     S.updateNext();
   }
 }
 
 void InstructionTables::printReport(llvm::raw_ostream &OS) const {
   for (const std::unique_ptr<View> &V : Views)
     V->printView(OS);
 }
 
 } // namespace mca

llvm/trunk/tools/llvm-mca/LSUnit.h

 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include <set>
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 
+class InstRef;
 struct InstrDesc;
 
 /// A Load/Store Unit implementing a load and store queues.
 ///
 /// This class implements a load queue and a store queue to emulate the
 /// out-of-order execution of memory operations.
 /// Each load (or store) consumes an entry in the load (or store) queue.
 ///

 #endif
 
   bool isSQEmpty() const { return StoreQueue.empty(); }
   bool isLQEmpty() const { return LoadQueue.empty(); }
   bool isSQFull() const { return SQ_Size != 0 && StoreQueue.size() == SQ_Size; }
   bool isLQFull() const { return LQ_Size != 0 && LoadQueue.size() == LQ_Size; }
 
   // Returns true if this instruction has been successfully enqueued.
-  bool reserve(unsigned Index, const InstrDesc &Desc);
+  bool reserve(const InstRef &IR);
 
   // The rules are:
   // 1. A store may not pass a previous store.
   // 2. A load may not pass a previous store unless flag 'NoAlias' is set.
   // 3. A load may pass a previous load.
   // 4. A store may not pass a previous load (regardless of flag 'NoAlias').
   // 5. A load has to wait until an older load barrier is fully executed.
   // 6. A store has to wait until an older store barrier is fully executed.
-  bool isReady(unsigned Index) const;
-  void onInstructionExecuted(unsigned Index);
+  bool isReady(const InstRef &IR) const;
+  void onInstructionExecuted(const InstRef &IR);
 };
 } // namespace mca
 
 #endif

llvm/trunk/tools/llvm-mca/LSUnit.cpp

void LSUnit::assignSQSlot(unsigned Index) {
   assert(!isSQFull());
   assert(StoreQueue.count(Index) == 0);
 
   DEBUG(dbgs() << "[LSUnit] - AssignSQSlot <Idx=" << Index
                << ",slot=" << StoreQueue.size() << ">\n");
   StoreQueue.insert(Index);
 }
 
-bool LSUnit::reserve(unsigned Index, const InstrDesc &Desc) {
+bool LSUnit::reserve(const InstRef &IR) {
+  const InstrDesc Desc = IR.getInstruction()->getDesc();
   unsigned MayLoad = Desc.MayLoad;
   unsigned MayStore = Desc.MayStore;
   unsigned IsMemBarrier = Desc.HasSideEffects;
   if (!MayLoad && !MayStore)
     return false;
 
+  const unsigned Index = IR.getSourceIndex();
   if (MayLoad) {
     if (IsMemBarrier)
       LoadBarriers.insert(Index);
     assignLQSlot(Index);
   }
   if (MayStore) {
     if (IsMemBarrier)
       StoreBarriers.insert(Index);
     assignSQSlot(Index);
   }
   return true;
 }
 
-bool LSUnit::isReady(unsigned Index) const {
+bool LSUnit::isReady(const InstRef &IR) const {
+  const unsigned Index = IR.getSourceIndex();
   bool IsALoad = LoadQueue.count(Index) != 0;
   bool IsAStore = StoreQueue.count(Index) != 0;
   assert((IsALoad || IsAStore) && "Instruction is not in queue!");
 
   unsigned LoadBarrierIndex = LoadBarriers.empty() ? 0 : *LoadBarriers.begin();
   unsigned StoreBarrierIndex =
       StoreBarriers.empty() ? 0 : *StoreBarriers.begin();
 
bool LSUnit::isReady(const InstRef &IR) const {
   // Check if there are no older loads.
   if (Index <= *LoadQueue.begin())
     return true;
 
   // There is at least one younger load.
   return !IsAStore;
 }
 
-void LSUnit::onInstructionExecuted(unsigned Index) {
+void LSUnit::onInstructionExecuted(const InstRef &IR) {
+  const unsigned Index = IR.getSourceIndex();
   std::set<unsigned>::iterator it = LoadQueue.find(Index);
   if (it != LoadQueue.end()) {
     DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << Index
                  << " has been removed from the load queue.\n");
     LoadQueue.erase(it);
   }
 
   it = StoreQueue.find(Index);

llvm/trunk/tools/llvm-mca/ResourcePressureView.cpp

void ResourcePressureView::initialize() {
   std::fill(ResourceUsage.begin(), ResourceUsage.end(), 0.0);
 }
 
 void ResourcePressureView::onInstructionEvent(const HWInstructionEvent &Event) {
   // We're only interested in Issue events.
   if (Event.Type != HWInstructionEvent::Issued)
     return;
   const auto &IssueEvent = static_cast<const HWInstructionIssuedEvent &>(Event);
-  unsigned SourceIdx = Event.Index % Source.size();
+  const unsigned SourceIdx = Event.IR.getSourceIndex() % Source.size();
   for (const std::pair<ResourceRef, double> &Use : IssueEvent.UsedResources) {
     const ResourceRef &RR = Use.first;
     assert(Resource2VecIndex.find(RR.first) != Resource2VecIndex.end());
     unsigned R2VIndex = Resource2VecIndex[RR.first];
     R2VIndex += countTrailingZeros(RR.second);
     ResourceUsage[R2VIndex + NumResourceUnits * SourceIdx] += Use.second;
     ResourceUsage[R2VIndex + NumResourceUnits * Source.size()] += Use.second;
   }

llvm/trunk/tools/llvm-mca/RetireControlUnit.h

struct RetireControlUnit {
   //
   // 'NumSlots' represents the number of entries consumed by the instruction in
   // the reorder buffer. Those entries will become available again once the
   // instruction is retired.
   //
   // Note that the size of the reorder buffer is defined by the scheduling
   // model via field 'NumMicroOpBufferSize'.
   struct RUToken {
-    unsigned Index;    // Instruction index.
+    InstRef IR;
     unsigned NumSlots; // Slots reserved to this instruction.
     bool Executed;     // True if the instruction is past the WB stage.
   };
 
 private:
   unsigned NextAvailableSlotIdx;
   unsigned CurrentInstructionSlotIdx;
   unsigned AvailableSlots;
bool isAvailable(unsigned Quantity = 1) const {
     // Some instructions may declare a number of uOps which exceedes the size
     // of the reorder buffer. To avoid problems, cap the amount of slots to
     // the size of the reorder buffer.
     Quantity = std::min(Quantity, static_cast<unsigned>(Queue.size()));
     return AvailableSlots >= Quantity;
   }
 
   // Reserves a number of slots, and returns a new token.
-  unsigned reserveSlot(unsigned Index, unsigned NumMicroOps);
+  unsigned reserveSlot(const InstRef &IS, unsigned NumMicroOps);
 
   /// Retires instructions in program order.
   void cycleEvent();
 
   void onInstructionExecuted(unsigned TokenID);
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 
 } // namespace mca
 
 #endif // LLVM_TOOLS_LLVM_MCA_RETIRE_CONTROL_UNIT_H

llvm/trunk/tools/llvm-mca/RetireControlUnit.cpp

if (SM.hasExtraProcessorInfo()) {
     MaxRetirePerCycle = EPI.MaxRetirePerCycle;
   }
 
   assert(AvailableSlots && "Invalid reorder buffer size!");
   Queue.resize(AvailableSlots);
 }
 
 // Reserves a number of slots, and returns a new token.
-unsigned RetireControlUnit::reserveSlot(unsigned Index, unsigned NumMicroOps) {
+unsigned RetireControlUnit::reserveSlot(const InstRef &IR, unsigned NumMicroOps) {
   assert(isAvailable(NumMicroOps));
   unsigned NormalizedQuantity =
       std::min(NumMicroOps, static_cast<unsigned>(Queue.size()));
   // Zero latency instructions may have zero mOps. Artificially bump this
   // value to 1. Although zero latency instructions don't consume scheduler
   // resources, they still consume one slot in the retire queue.
   NormalizedQuantity = std::max(NormalizedQuantity, 1U);
   unsigned TokenID = NextAvailableSlotIdx;
-  Queue[NextAvailableSlotIdx] = {Index, NormalizedQuantity, false};
+  Queue[NextAvailableSlotIdx] = {IR, NormalizedQuantity, false};
   NextAvailableSlotIdx += NormalizedQuantity;
   NextAvailableSlotIdx %= Queue.size();
   AvailableSlots -= NormalizedQuantity;
   return TokenID;
 }
 
 void RetireControlUnit::cycleEvent() {
   if (isEmpty())
     return;
 
   unsigned NumRetired = 0;
   while (!isEmpty()) {
     if (MaxRetirePerCycle != 0 && NumRetired == MaxRetirePerCycle)
       break;
     RUToken &Current = Queue[CurrentInstructionSlotIdx];
     assert(Current.NumSlots && "Reserved zero slots?");
+    assert(Current.IR.isValid() && "Invalid RUToken in the RCU queue.");
     if (!Current.Executed)
       break;
-    Owner->notifyInstructionRetired(Current.Index);
+    Owner->notifyInstructionRetired(Current.IR);
     CurrentInstructionSlotIdx += Current.NumSlots;
     CurrentInstructionSlotIdx %= Queue.size();
     AvailableSlots += Current.NumSlots;
     NumRetired++;
   }
 }
 
 void RetireControlUnit::onInstructionExecuted(unsigned TokenID) {
   assert(Queue.size() > TokenID);
-  assert(Queue[TokenID].Executed == false && Queue[TokenID].Index != ~0U);
+  assert(Queue[TokenID].Executed == false && Queue[TokenID].IR.isValid());
   Queue[TokenID].Executed = true;
 }
 
 #ifndef NDEBUG
 void RetireControlUnit::dump() const {
   dbgs() << "Retire Unit: { Total Slots=" << Queue.size()
          << ", Available Slots=" << AvailableSlots << " }\n";
 }
 #endif
 
 } // namespace mca

llvm/trunk/tools/llvm-mca/Scheduler.h

class Scheduler {
   DispatchUnit *DU;
 
   using QueueEntryTy = std::pair<unsigned, Instruction *>;
   std::map<unsigned, Instruction *> WaitQueue;
   std::map<unsigned, Instruction *> ReadyQueue;
   std::map<unsigned, Instruction *> IssuedQueue;
 
   void
-  notifyInstructionIssued(unsigned Index,
+  notifyInstructionIssued(const InstRef &IR,
                           llvm::ArrayRef<std::pair<ResourceRef, double>> Used);
-  void notifyInstructionExecuted(unsigned Index);
-  void notifyInstructionReady(unsigned Index);
+  void notifyInstructionExecuted(const InstRef &IR);
+  void notifyInstructionReady(const InstRef &IR);
   void notifyResourceAvailable(const ResourceRef &RR);
 
   // Notify the Backend that buffered resources were consumed.
   void notifyReservedBuffers(llvm::ArrayRef<uint64_t> Buffers);
   // Notify the Backend that buffered resources were freed.
   void notifyReleasedBuffers(llvm::ArrayRef<uint64_t> Buffers);
 
   /// Select the next instruction to issue from the ReadyQueue.
   /// This method gives priority to older instructions.
-  std::pair<unsigned, Instruction *> select();
+  InstRef select();
 
   /// Move instructions from the WaitQueue to the ReadyQueue if input operands
   /// are all available.
-  void promoteToReadyQueue(llvm::SmallVectorImpl<unsigned> &Ready);
+  void promoteToReadyQueue(llvm::SmallVectorImpl<InstRef> &Ready);
 
   /// Issue an instruction without updating the ready queue.
   void issueInstructionImpl(
-      unsigned Index, Instruction &IS,
+      InstRef &IR,
       llvm::SmallVectorImpl<std::pair<ResourceRef, double>> &Pipes);
 
-  void updatePendingQueue(llvm::SmallVectorImpl<unsigned> &Ready);
-  void updateIssuedQueue(llvm::SmallVectorImpl<unsigned> &Executed);
+  void updatePendingQueue(llvm::SmallVectorImpl<InstRef> &Ready);
+  void updateIssuedQueue(llvm::SmallVectorImpl<InstRef> &Executed);
 
 public:
   Scheduler(Backend *B, const llvm::MCSchedModel &Model, unsigned LoadQueueSize,
             unsigned StoreQueueSize, bool AssumeNoAlias)
       : SM(Model), Resources(llvm::make_unique<ResourceManager>(SM)),
         LSU(llvm::make_unique<LSUnit>(LoadQueueSize, StoreQueueSize,
                                       AssumeNoAlias)),
         Owner(B) {}
 
   void setDispatchUnit(DispatchUnit *DispUnit) { DU = DispUnit; }
 
-  /// Check if instruction at index Idx can be dispatched.
+  /// Check if the instruction in 'IR' can be dispatched.
   ///
   /// The DispatchUnit is responsible for querying the Scheduler before
   /// dispatching new instructions. Queries are performed through method
   /// `Scheduler::CanBeDispatched`. If scheduling resources are available,
   /// and the instruction can be dispatched, then this method returns true.
   /// Otherwise, a generic HWStallEvent is notified to the listeners.
-  bool canBeDispatched(unsigned Idx, const InstrDesc &Desc) const;
-  void scheduleInstruction(unsigned Idx, Instruction &MCIS);
+  bool canBeDispatched(const InstRef &IR) const;
+  void scheduleInstruction(InstRef &IR);
 
   /// Issue an instruction.
-  void issueInstruction(unsigned Index, Instruction &IS);
+  void issueInstruction(InstRef &IR);
 
   /// Reserve one entry in each buffered resource.
   void reserveBuffers(llvm::ArrayRef<uint64_t> Buffers) {
     Resources->reserveBuffers(Buffers);
   }
 
   /// Release buffer entries previously allocated by method reserveBuffers.
   void releaseBuffers(llvm::ArrayRef<uint64_t> Buffers) {

llvm/trunk/tools/llvm-mca/Scheduler.cpp

if (!BR.second) {
       ResourcesFreed.push_back(RR);
     }
   }
 
   for (const ResourceRef &RF : ResourcesFreed)
     BusyResources.erase(RF);
 }
 
-void Scheduler::scheduleInstruction(unsigned Idx, Instruction &MCIS) {
+void Scheduler::scheduleInstruction(InstRef &IR) {
+  const unsigned Idx = IR.getSourceIndex();
   assert(WaitQueue.find(Idx) == WaitQueue.end());
   assert(ReadyQueue.find(Idx) == ReadyQueue.end());
   assert(IssuedQueue.find(Idx) == IssuedQueue.end());
 
   // Reserve a slot in each buffered resource. Also, mark units with
   // BufferSize=0 as reserved. Resources with a buffer size of zero will only
   // be released after MCIS is issued, and all the ResourceCycles for those
   // units have been consumed.
-  const InstrDesc &Desc = MCIS.getDesc();
+  const InstrDesc &Desc = IR.getInstruction()->getDesc();
   reserveBuffers(Desc.Buffers);
   notifyReservedBuffers(Desc.Buffers);
 
   // If necessary, reserve queue entries in the load-store unit (LSU).
-  bool Reserved = LSU->reserve(Idx, Desc);
-  if (!MCIS.isReady() || (Reserved && !LSU->isReady(Idx))) {
+  bool Reserved = LSU->reserve(IR);
+  if (!IR.getInstruction()->isReady() || (Reserved && !LSU->isReady(IR))) {
     DEBUG(dbgs() << "[SCHEDULER] Adding " << Idx << " to the Wait Queue\n");
-    WaitQueue[Idx] = &MCIS;
+    WaitQueue[Idx] = IR.getInstruction();
     return;
   }
-  notifyInstructionReady(Idx);
+  notifyInstructionReady(IR);
 
   // Don't add a zero-latency instruction to the Wait or Ready queue.
   // A zero-latency instruction doesn't consume any scheduler resources. That is
   // because it doesn't need to be executed, and it is often removed at register
   // renaming stage. For example, register-register moves are often optimized at
   // register renaming stage by simply updating register aliases. On some
   // targets, zero-idiom instructions (for example: a xor that clears the value
   // of a register) are treated speacially, and are often eliminated at register
   // renaming stage.
   bool IsZeroLatency = !Desc.MaxLatency && Desc.Resources.empty();
 
   // Instructions that use an in-order dispatch/issue processor resource must be
   // issued immediately to the pipeline(s). Any other in-order buffered
   // resources (i.e. BufferSize=1) is consumed.
 
   if (!IsZeroLatency && !Resources->mustIssueImmediately(Desc)) {
-    DEBUG(dbgs() << "[SCHEDULER] Adding " << Idx << " to the Ready Queue\n");
-    ReadyQueue[Idx] = &MCIS;
+    DEBUG(dbgs() << "[SCHEDULER] Adding " << IR << " to the Ready Queue\n");
+    ReadyQueue[IR.getSourceIndex()] = IR.getInstruction();
     return;
   }
 
-  DEBUG(dbgs() << "[SCHEDULER] Instruction " << Idx << " issued immediately\n");
+  DEBUG(dbgs() << "[SCHEDULER] Instruction " << IR << " issued immediately\n");
   // Release buffered resources and issue MCIS to the underlying pipelines.
-  issueInstruction(Idx, MCIS);
+  issueInstruction(IR);
 }
 
 void Scheduler::cycleEvent() {
   SmallVector<ResourceRef, 8> ResourcesFreed;
   Resources->cycleEvent(ResourcesFreed);
 
   for (const ResourceRef &RR : ResourcesFreed)
     notifyResourceAvailable(RR);
 
-  SmallVector<unsigned, 4> InstructionIDs;
+  SmallVector<InstRef, 4> InstructionIDs;
   updateIssuedQueue(InstructionIDs);
-  for (unsigned Idx : InstructionIDs)
-    notifyInstructionExecuted(Idx);
+  for (const InstRef &IR : InstructionIDs)
+    notifyInstructionExecuted(IR);
   InstructionIDs.clear();
 
   updatePendingQueue(InstructionIDs);
-  for (unsigned Idx : InstructionIDs)
-    notifyInstructionReady(Idx);
+  for (const InstRef &IR : InstructionIDs)
+    notifyInstructionReady(IR);
   InstructionIDs.clear();
 
-  std::pair<unsigned, Instruction *> Inst = select();
-  while (Inst.second) {
-    issueInstruction(Inst.first, *Inst.second);
+  InstRef IR = select();
+  while (IR.isValid()) {
+    issueInstruction(IR);
 
     // Instructions that have been issued during this cycle might have unblocked
     // other dependent instructions. Dependent instructions may be issued during
     // this same cycle if operands have ReadAdvance entries.  Promote those
     // instructions to the ReadyQueue and tell to the caller that we need
     // another round of 'issue()'.
     promoteToReadyQueue(InstructionIDs);
-    for (unsigned Idx : InstructionIDs)
-      notifyInstructionReady(Idx);
+    for (const InstRef &I : InstructionIDs)
+      notifyInstructionReady(I);
     InstructionIDs.clear();
 
     // Select the next instruction to issue.
-    Inst = select();
+    IR = select();
   }
 }
 
 #ifndef NDEBUG
 void Scheduler::dump() const {
   dbgs() << "[SCHEDULER]: WaitQueue size is: " << WaitQueue.size() << '\n';
   dbgs() << "[SCHEDULER]: ReadyQueue size is: " << ReadyQueue.size() << '\n';
   dbgs() << "[SCHEDULER]: IssuedQueue size is: " << IssuedQueue.size() << '\n';
   Resources->dump();
 }
 #endif
 
-bool Scheduler::canBeDispatched(unsigned Index, const InstrDesc &Desc) const {
+bool Scheduler::canBeDispatched(const InstRef &IR) const {
   HWStallEvent::GenericEventType Type = HWStallEvent::Invalid;
+  const InstrDesc &Desc = IR.getInstruction()->getDesc();
 
   if (Desc.MayLoad && LSU->isLQFull())
     Type = HWStallEvent::LoadQueueFull;
   else if (Desc.MayStore && LSU->isSQFull())
     Type = HWStallEvent::StoreQueueFull;
   else {
     switch (Resources->canBeDispatched(Desc.Buffers)) {
     default:
       return true;
     case ResourceStateEvent::RS_BUFFER_UNAVAILABLE:
       Type = HWStallEvent::SchedulerQueueFull;
       break;
     case ResourceStateEvent::RS_RESERVED:
       Type = HWStallEvent::DispatchGroupStall;
     }
   }
 
-  Owner->notifyStallEvent(HWStallEvent(Type, Index));
+  Owner->notifyStallEvent(HWStallEvent(Type, IR));
   return false;
 }
 
 void Scheduler::issueInstructionImpl(
-    unsigned InstrIndex, Instruction &IS,
+    InstRef &IR,
     SmallVectorImpl<std::pair<ResourceRef, double>> &UsedResources) {
-  const InstrDesc &D = IS.getDesc();
+  Instruction *IS = IR.getInstruction();
+  const InstrDesc &D = IS->getDesc();
 
   // Issue the instruction and collect all the consumed resources
   // into a vector. That vector is then used to notify the listener.
   Resources->issueInstruction(D, UsedResources);
 
   // Notify the instruction that it started executing.
   // This updates the internal state of each write.
-  IS.execute();
+  IS->execute();
 
-  if (IS.isExecuting())
-    IssuedQueue[InstrIndex] = &IS;
+  if (IS->isExecuting())
+    IssuedQueue[IR.getSourceIndex()] = IS;
 }
 
-void Scheduler::issueInstruction(unsigned InstrIndex, Instruction &IS) {
+void Scheduler::issueInstruction(InstRef &IR) {
   // Release buffered resources.
-  const InstrDesc &Desc = IS.getDesc();
+  const InstrDesc &Desc = IR.getInstruction()->getDesc();
   releaseBuffers(Desc.Buffers);
   notifyReleasedBuffers(Desc.Buffers);
 
   // Issue IS to the underlying pipelines and notify listeners.
   SmallVector<std::pair<ResourceRef, double>, 4> Pipes;
-  issueInstructionImpl(InstrIndex, IS, Pipes);
-  notifyInstructionIssued(InstrIndex, Pipes);
-  if (IS.isExecuted())
-    notifyInstructionExecuted(InstrIndex);
+  issueInstructionImpl(IR, Pipes);
+  notifyInstructionIssued(IR, Pipes);
+  if (IR.getInstruction()->isExecuted())
+    notifyInstructionExecuted(IR);
 }
 
-void Scheduler::promoteToReadyQueue(SmallVectorImpl<unsigned> &Ready) {
+void Scheduler::promoteToReadyQueue(SmallVectorImpl<InstRef> &Ready) {
   // Scan the set of waiting instructions and promote them to the
   // ready queue if operands are all ready.
   for (auto I = WaitQueue.begin(), E = WaitQueue.end(); I != E;) {
-    const QueueEntryTy &Entry = *I;
-    unsigned IID = Entry.first;
-    Instruction &Inst = *Entry.second;
+    const unsigned IID = I->first;
+    Instruction *IS = I->second;
 
     // Check if this instruction is now ready. In case, force
     // a transition in state using method 'update()'.
-    Inst.update();
+    IS->update();
 
-    const InstrDesc &Desc = Inst.getDesc();
+    const InstrDesc &Desc = IS->getDesc();
     bool IsMemOp = Desc.MayLoad || Desc.MayStore;
-    if (!Inst.isReady() || (IsMemOp && !LSU->isReady(IID))) {
+    if (!IS->isReady() || (IsMemOp && !LSU->isReady({IID, IS}))) {
       ++I;
       continue;
     }
 
-    Ready.emplace_back(IID);
-    ReadyQueue[IID] = &Inst;
+    Ready.emplace_back(IID, IS);
+    ReadyQueue[IID] = IS;
     auto ToRemove = I;
     ++I;
     WaitQueue.erase(ToRemove);
   }
 }
 
-std::pair<unsigned, Instruction *> Scheduler::select() {
+InstRef Scheduler::select() {
   // Give priority to older instructions in the ReadyQueue. Since the ready
   // queue is ordered by key, this will always prioritize older instructions.
   const auto It = std::find_if(ReadyQueue.begin(), ReadyQueue.end(),
                                [&](const QueueEntryTy &Entry) {
-                                 const Instruction &IS = *Entry.second;
-                                 const InstrDesc &D = IS.getDesc();
+                                 const InstrDesc &D = Entry.second->getDesc();
                                  return Resources->canBeIssued(D);
                                });
 
   if (It == ReadyQueue.end())
     return {0, nullptr};
 
   // We found an instruction to issue.
-  const QueueEntryTy Entry = *It;
+  InstRef IR(It->first, It->second);
   ReadyQueue.erase(It);
-  return Entry;
+  return IR;
 }
 
-void Scheduler::updatePendingQueue(SmallVectorImpl<unsigned> &Ready) {
+void Scheduler::updatePendingQueue(SmallVectorImpl<InstRef> &Ready) {
   // Notify to instructions in the pending queue that a new cycle just
   // started.
   for (QueueEntryTy Entry : WaitQueue)
     Entry.second->cycleEvent();
   promoteToReadyQueue(Ready);
 }
 
-void Scheduler::updateIssuedQueue(SmallVectorImpl<unsigned> &Executed) {
+void Scheduler::updateIssuedQueue(SmallVectorImpl<InstRef> &Executed) {
   for (auto I = IssuedQueue.begin(), E = IssuedQueue.end(); I != E;) {
     const QueueEntryTy Entry = *I;
-    Entry.second->cycleEvent();
-    if (Entry.second->isExecuted()) {
-      Executed.push_back(Entry.first);
+    Instruction *IS = Entry.second;
+    IS->cycleEvent();
+    if (IS->isExecuted()) {
+      Executed.push_back({Entry.first, Entry.second});
       auto ToRemove = I;
       ++I;
       IssuedQueue.erase(ToRemove);
     } else {
       DEBUG(dbgs() << "[SCHEDULER]: Instruction " << Entry.first
                    << " is still executing.\n");
       ++I;
     }
   }
 }
 
 void Scheduler::notifyInstructionIssued(
-    unsigned Index, ArrayRef<std::pair<ResourceRef, double>> Used) {
+    const InstRef &IR, ArrayRef<std::pair<ResourceRef, double>> Used) {
   DEBUG({
-    dbgs() << "[E] Instruction Issued: " << Index << '\n';
+    dbgs() << "[E] Instruction Issued: " << IR << '\n';
     for (const std::pair<ResourceRef, unsigned> &Resource : Used) {
       dbgs() << "[E] Resource Used: [" << Resource.first.first << '.'
              << Resource.first.second << "]\n";
       dbgs() << "           cycles: " << Resource.second << '\n';
     }
   });
-  Owner->notifyInstructionEvent(HWInstructionIssuedEvent(Index, Used));
+  Owner->notifyInstructionEvent(HWInstructionIssuedEvent(IR, Used));
 }
 
-void Scheduler::notifyInstructionExecuted(unsigned Index) {
-  LSU->onInstructionExecuted(Index);
-  DEBUG(dbgs() << "[E] Instruction Executed: " << Index << '\n');
+void Scheduler::notifyInstructionExecuted(const InstRef &IR) {
+  LSU->onInstructionExecuted(IR);
+  DEBUG(dbgs() << "[E] Instruction Executed: " << IR << '\n');
   Owner->notifyInstructionEvent(
-      HWInstructionEvent(HWInstructionEvent::Executed, Index));
-
-  const Instruction &IS = Owner->getInstruction(Index);
-  DU->onInstructionExecuted(IS.getRCUTokenID());
+      HWInstructionEvent(HWInstructionEvent::Executed, IR));
+  DU->onInstructionExecuted(IR.getInstruction()->getRCUTokenID());
 }
 
-void Scheduler::notifyInstructionReady(unsigned Index) {
-  DEBUG(dbgs() << "[E] Instruction Ready: " << Index << '\n');
+void Scheduler::notifyInstructionReady(const InstRef &IR) {
+  DEBUG(dbgs() << "[E] Instruction Ready: " << IR << '\n');
   Owner->notifyInstructionEvent(
-      HWInstructionEvent(HWInstructionEvent::Ready, Index));
+      HWInstructionEvent(HWInstructionEvent::Ready, IR));
 }
 
 void Scheduler::notifyResourceAvailable(const ResourceRef &RR) {
   Owner->notifyResourceAvailable(RR);
 }
 
 void Scheduler::notifyReservedBuffers(ArrayRef<uint64_t> Buffers) {
   if (Buffers.empty())

llvm/trunk/tools/llvm-mca/SourceMgr.h

 #ifndef LLVM_TOOLS_LLVM_MCA_SOURCEMGR_H
 #define LLVM_TOOLS_LLVM_MCA_SOURCEMGR_H
 
 #include "llvm/MC/MCInst.h"
 #include <vector>
 
 namespace mca {
 
-typedef std::pair<unsigned, const llvm::MCInst *> InstRef;
+typedef std::pair<unsigned, const llvm::MCInst *> SourceRef;
 
 class SourceMgr {
   using InstVec = std::vector<std::unique_ptr<const llvm::MCInst>>;
   const InstVec &Sequence;
   unsigned Current;
   unsigned Iterations;
   static const unsigned DefaultIterations = 100;
 
 public:
   SourceMgr(const InstVec &MCInstSequence, unsigned NumIterations)
       : Sequence(MCInstSequence), Current(0),
         Iterations(NumIterations ? NumIterations : DefaultIterations) {}
 
   unsigned getCurrentIteration() const { return Current / Sequence.size(); }
   unsigned getNumIterations() const { return Iterations; }
   unsigned size() const { return Sequence.size(); }
   const InstVec &getSequence() const { return Sequence; }
 
   bool hasNext() { return Current < (Iterations * size()); }
   void updateNext() { Current++; }
 
-  const InstRef peekNext() const {
+  const SourceRef peekNext() const {
     unsigned Index = getCurrentInstructionIndex();
-    return InstRef(Current, Sequence[Index].get());
+    return SourceRef(Current, Sequence[Index].get());
   }
 
   unsigned getCurrentInstructionIndex() const {
     return Current % Sequence.size();
   }
 
   const llvm::MCInst &getMCInstFromIndex(unsigned Index) const {
     return *Sequence[Index % size()];
   }
 
   bool isEmpty() const { return size() == 0; }
 };
 } // namespace mca
 
 #endif

llvm/trunk/tools/llvm-mca/TimelineView.cpp

void TimelineView::initialize(unsigned MaxIterations) {
   std::fill(Timeline.begin(), Timeline.end(), NullTVEntry);
 
   WaitTime.resize(AsmSequence.size());
   WaitTimeEntry NullWTEntry = {0, 0, 0, 0};
   std::fill(WaitTime.begin(), WaitTime.end(), NullWTEntry);
 }
 
 void TimelineView::onInstructionEvent(const HWInstructionEvent &Event) {
-  if (CurrentCycle >= MaxCycle || Event.Index >= Timeline.size())
+  const unsigned Index = Event.IR.getSourceIndex();
+  if (CurrentCycle >= MaxCycle || Index >= Timeline.size())
     return;
   switch (Event.Type) {
   case HWInstructionEvent::Retired: {
-    TimelineViewEntry &TVEntry = Timeline[Event.Index];
+    TimelineViewEntry &TVEntry = Timeline[Index];
     TVEntry.CycleRetired = CurrentCycle;
 
     // Update the WaitTime entry which corresponds to this Index.
-    WaitTimeEntry &WTEntry = WaitTime[Event.Index % AsmSequence.size()];
+    WaitTimeEntry &WTEntry = WaitTime[Index % AsmSequence.size()];
     WTEntry.Executions++;
     WTEntry.CyclesSpentInSchedulerQueue +=
         TVEntry.CycleIssued - TVEntry.CycleDispatched;
     assert(TVEntry.CycleDispatched <= TVEntry.CycleReady);
     WTEntry.CyclesSpentInSQWhileReady +=
         TVEntry.CycleIssued - TVEntry.CycleReady;
     WTEntry.CyclesSpentAfterWBAndBeforeRetire +=
         (TVEntry.CycleRetired - 1) - TVEntry.CycleExecuted;
     break;
   }
   case HWInstructionEvent::Ready:
-    Timeline[Event.Index].CycleReady = CurrentCycle;
+    Timeline[Index].CycleReady = CurrentCycle;
     break;
   case HWInstructionEvent::Issued:
-    Timeline[Event.Index].CycleIssued = CurrentCycle;
+    Timeline[Index].CycleIssued = CurrentCycle;
     break;
   case HWInstructionEvent::Executed:
-    Timeline[Event.Index].CycleExecuted = CurrentCycle;
+    Timeline[Index].CycleExecuted = CurrentCycle;
     break;
   case HWInstructionEvent::Dispatched:
-    Timeline[Event.Index].CycleDispatched = CurrentCycle;
+    Timeline[Index].CycleDispatched = CurrentCycle;
     break;
   default:
     return;
   }
   LastCycle = std::max(LastCycle, CurrentCycle);
 }
 
 static void printAverageTime(raw_string_ostream &OS, double AverageTime) {