[mips] Add support for Global INValidate ASE

[vstefanovic]

Summary

This includes

Instructions: ginvi, ginvt,

Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv

Attribute: ginv

.MIPS.abiflags: GINV (0x20000)

[sdardis]

Where's the ginvgt instruction defined? I'm not seeing in it the manuals.

[vstefanovic]

That's a good question, I only found it in Faraz's binutils patch, and used that as a reference.

[sdardis]

The ginvgt instruction can be removed until the documentation is updated.

[vstefanovic]

Removed the undocumented gingvt instruction.

[sdardis]

lib/Target/Mips/MicroMips32r6InstrFormats.td

899 ↗

(On Diff #146830)

Split this range up into the fields as specified by the arch reference manual.

901 ↗

(On Diff #146830)

Likewise.

lib/Target/Mips/Mips32r6InstrFormats.td

601 ↗

(On Diff #146830)

This is missing bits 20-10.

lib/Target/Mips/Mips32r6InstrInfo.td

834 ↗

(On Diff #146830)

Indent this line so that InstrItinClass is directly underneath the 'string' in the line above.

840 ↗

(On Diff #146830)

Also requires 'bit hasSideEffects = 1;'

[vstefanovic]

Addressed inline comments.

[vstefanovic]

lib/Target/Mips/MicroMips32r6InstrFormats.td

901 ↗

(On Diff #146830)

I don't have the manual at hand, I hope I guessed it right.

[sdardis]

LGTM.

llvm/trunk/include/llvm/Support/MipsABIFlags.h

enum AFL_ASE {
   AFL_ASE_MIPS3D = 0x00000020,    // MIPS-3D ASE
   AFL_ASE_MT = 0x00000040,        // MT ASE
   AFL_ASE_SMARTMIPS = 0x00000080, // SmartMIPS ASE
   AFL_ASE_VIRT = 0x00000100,      // VZ ASE
   AFL_ASE_MSA = 0x00000200,       // MSA ASE
   AFL_ASE_MIPS16 = 0x00000400,    // MIPS16 ASE
   AFL_ASE_MICROMIPS = 0x00000800, // MICROMIPS ASE
   AFL_ASE_XPA = 0x00001000,       // XPA ASE
-  AFL_ASE_CRC = 0x00008000        // CRC ASE
+  AFL_ASE_CRC = 0x00008000,       // CRC ASE
+  AFL_ASE_GINV = 0x00020000       // GINV ASE
 };
 
 // Values for the isa_ext word of an ABI flags structure.
 enum AFL_EXT {
   AFL_EXT_NONE = 0,         // None
   AFL_EXT_XLR = 1,          // RMI Xlr instruction
   AFL_EXT_OCTEON2 = 2,      // Cavium Networks Octeon2
   AFL_EXT_OCTEONP = 3,      // Cavium Networks OcteonP

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

#include "MipsGenAsmMatcher.inc"
   bool parseSetPopDirective();
   bool parseSetPushDirective();
   bool parseSetSoftFloatDirective();
   bool parseSetHardFloatDirective();
   bool parseSetMtDirective();
   bool parseSetNoMtDirective();
   bool parseSetNoCRCDirective();
   bool parseSetNoVirtDirective();
+  bool parseSetNoGINVDirective();
 
   bool parseSetAssignment();
 
   bool parseDataDirective(unsigned Size, SMLoc L);
   bool parseDirectiveGpWord();
   bool parseDirectiveGpDWord();
   bool parseDirectiveDtpRelWord();
   bool parseDirectiveDtpRelDWord();
#undef GET_OPERAND_DIAGNOSTIC_TYPES
   bool hasCRC() const {
     return getSTI().getFeatureBits()[Mips::FeatureCRC];
   }
 
   bool hasVirt() const {
     return getSTI().getFeatureBits()[Mips::FeatureVirt];
   }
 
+  bool hasGINV() const {
+    return getSTI().getFeatureBits()[Mips::FeatureGINV];
+  }
+
   /// Warn if RegIndex is the same as the current AT.
   void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
 
   void warnIfNoMacro(SMLoc Loc);
 
   bool isLittle() const { return IsLittleEndian; }
 
   const MCExpr *createTargetUnaryExpr(const MCExpr *E,
bool MipsAsmParser::parseSetNoVirtDirective() {
 
   clearFeatureBits(Mips::FeatureVirt, "virt");
 
   getTargetStreamer().emitDirectiveSetNoVirt();
   Parser.Lex(); // Consume the EndOfStatement.
   return false;
 }
 
+bool MipsAsmParser::parseSetNoGINVDirective() {
+  MCAsmParser &Parser = getParser();
+  Parser.Lex(); // Eat "noginv".
+
+  // If this is not the end of the statement, report an error.
+  if (getLexer().isNot(AsmToken::EndOfStatement)) {
+    reportParseError("unexpected token, expected end of statement");
+    return false;
+  }
+
+  clearFeatureBits(Mips::FeatureGINV, "ginv");
+
+  getTargetStreamer().emitDirectiveSetNoGINV();
+  Parser.Lex(); // Consume the EndOfStatement.
+  return false;
+}
+
 bool MipsAsmParser::parseSetPopDirective() {
   MCAsmParser &Parser = getParser();
   SMLoc Loc = getLexer().getLoc();
 
   Parser.Lex();
   if (getLexer().isNot(AsmToken::EndOfStatement))
     return reportParseError("unexpected token, expected end of statement");
 
bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
   case Mips::FeatureCRC:
     setFeatureBits(Mips::FeatureCRC, "crc");
     getTargetStreamer().emitDirectiveSetCRC();
     break;
   case Mips::FeatureVirt:
     setFeatureBits(Mips::FeatureVirt, "virt");
     getTargetStreamer().emitDirectiveSetVirt();
     break;
+  case Mips::FeatureGINV:
+    setFeatureBits(Mips::FeatureGINV, "ginv");
+    getTargetStreamer().emitDirectiveSetGINV();
+    break;
   }
   return false;
 }
 
 bool MipsAsmParser::eatComma(StringRef ErrorStr) {
   MCAsmParser &Parser = getParser();
   if (getLexer().isNot(AsmToken::Comma)) {
     SMLoc Loc = getLexer().getLoc();
bool MipsAsmParser::parseDirectiveSet() {
   } else if (Tok.getString() == "crc") {
     return parseSetFeature(Mips::FeatureCRC);
   } else if (Tok.getString() == "nocrc") {
     return parseSetNoCRCDirective();
   } else if (Tok.getString() == "virt") {
     return parseSetFeature(Mips::FeatureVirt);
   } else if (Tok.getString() == "novirt") {
     return parseSetNoVirtDirective();
+  } else if (Tok.getString() == "ginv") {
+    return parseSetFeature(Mips::FeatureGINV);
+  } else if (Tok.getString() == "noginv") {
+    return parseSetNoGINVDirective();
   } else {
     // It is just an identifier, look for an assignment.
     parseSetAssignment();
     return false;
   }
 
   return true;
 }

 ///  ::= .module fp=value
 ///  ::= .module softfloat
 ///  ::= .module hardfloat
 ///  ::= .module mt
 ///  ::= .module crc
 ///  ::= .module nocrc
 ///  ::= .module virt
 ///  ::= .module novirt
+///  ::= .module ginv
+///  ::= .module noginv
 bool MipsAsmParser::parseDirectiveModule() {
   MCAsmParser &Parser = getParser();
   MCAsmLexer &Lexer = getLexer();
   SMLoc L = Lexer.getLoc();
 
   if (!getTargetStreamer().isModuleDirectiveAllowed()) {
     // TODO : get a better message.
     reportParseError(".module directive must appear before any code");
if (Option == "oddspreg") {
 
     // If this is not the end of the statement, report an error.
     if (getLexer().isNot(AsmToken::EndOfStatement)) {
       reportParseError("unexpected token, expected end of statement");
       return false;
     }
 
     return false; // parseDirectiveModule has finished successfully.
+  } else if (Option == "ginv") {
+    setModuleFeatureBits(Mips::FeatureGINV, "ginv");
+
+    // Synchronize the ABI Flags information with the FeatureBits information we
+    // updated above.
+    getTargetStreamer().updateABIInfo(*this);
+
+    // If printing assembly, use the recently updated ABI Flags information.
+    // If generating ELF, don't do anything (the .MIPS.abiflags section gets
+    // emitted later).
+    getTargetStreamer().emitDirectiveModuleGINV();
+
+    // If this is not the end of the statement, report an error.
+    if (getLexer().isNot(AsmToken::EndOfStatement)) {
+      reportParseError("unexpected token, expected end of statement");
+      return false;
+    }
+
+    return false; // parseDirectiveModule has finished successfully.
+  } else if (Option == "noginv") {
+    clearModuleFeatureBits(Mips::FeatureGINV, "ginv");
+
+    // Synchronize the ABI Flags information with the FeatureBits information we
+    // updated above.
+    getTargetStreamer().updateABIInfo(*this);
+
+    // If printing assembly, use the recently updated ABI Flags information.
+    // If generating ELF, don't do anything (the .MIPS.abiflags section gets
+    // emitted later).
+    getTargetStreamer().emitDirectiveModuleNoGINV();
+
+    // If this is not the end of the statement, report an error.
+    if (getLexer().isNot(AsmToken::EndOfStatement)) {
+      reportParseError("unexpected token, expected end of statement");
+      return false;
+    }
+
+    return false; // parseDirectiveModule has finished successfully.
   } else {
     return Error(L, "'" + Twine(Option) + "' is not a valid .module option.");
   }
 }
 
 /// parseDirectiveModuleFP
 ///  ::= =32
 ///  ::= =xx

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h

void setASESetFromPredicates(const PredicateLibrary &P) {
     if (P.inMips16Mode())
       ASESet |= Mips::AFL_ASE_MIPS16;
     if (P.hasMT())
       ASESet |= Mips::AFL_ASE_MT;
     if (P.hasCRC())
       ASESet |= Mips::AFL_ASE_CRC;
     if (P.hasVirt())
       ASESet |= Mips::AFL_ASE_VIRT;
+    if (P.hasGINV())
+      ASESet |= Mips::AFL_ASE_GINV;
   }
 
   template <class PredicateLibrary>
   void setFpAbiFromPredicates(const PredicateLibrary &P) {
     Is32BitABI = P.isABI_O32();
 
     FpABI = FpABIKind::ANY;
     if (P.useSoftFloat())

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMt() {}
 void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetCRC() {}
 void MipsTargetStreamer::emitDirectiveSetNoCRC() {}
 void MipsTargetStreamer::emitDirectiveSetVirt() {}
 void MipsTargetStreamer::emitDirectiveSetNoVirt() {}
+void MipsTargetStreamer::emitDirectiveSetGINV() {}
+void MipsTargetStreamer::emitDirectiveSetNoGINV() {}
 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
   forbidModuleDirective();
 }
 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
 void MipsTargetStreamer::emitDirectiveAbiCalls() {}

 }
 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
 void MipsTargetStreamer::emitDirectiveModuleMT() {}
 void MipsTargetStreamer::emitDirectiveModuleCRC() {}
 void MipsTargetStreamer::emitDirectiveModuleNoCRC() {}
 void MipsTargetStreamer::emitDirectiveModuleVirt() {}
 void MipsTargetStreamer::emitDirectiveModuleNoVirt() {}
+void MipsTargetStreamer::emitDirectiveModuleGINV() {}
+void MipsTargetStreamer::emitDirectiveModuleNoGINV() {}
 void MipsTargetStreamer::emitDirectiveSetFp(
     MipsABIFlagsSection::FpABIKind Value) {
   forbidModuleDirective();
 }
 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
   forbidModuleDirective();
 }
void MipsTargetAsmStreamer::emitDirectiveSetVirt() {
   MipsTargetStreamer::emitDirectiveSetVirt();
 }
 
 void MipsTargetAsmStreamer::emitDirectiveSetNoVirt() {
   OS << "\t.set\tnovirt\n";
   MipsTargetStreamer::emitDirectiveSetNoVirt();
 }
 
+void MipsTargetAsmStreamer::emitDirectiveSetGINV() {
+  OS << "\t.set\tginv\n";
+  MipsTargetStreamer::emitDirectiveSetGINV();
+}
+
+void MipsTargetAsmStreamer::emitDirectiveSetNoGINV() {
+  OS << "\t.set\tnoginv\n";
+  MipsTargetStreamer::emitDirectiveSetNoGINV();
+}
+
 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
   OS << "\t.set\tat\n";
   MipsTargetStreamer::emitDirectiveSetAt();
 }
 
 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
   OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
   MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);

 void MipsTargetAsmStreamer::emitDirectiveModuleVirt() {
   OS << "\t.module\tvirt\n";
 }
 
 void MipsTargetAsmStreamer::emitDirectiveModuleNoVirt() {
   OS << "\t.module\tnovirt\n";
 }
 
+void MipsTargetAsmStreamer::emitDirectiveModuleGINV() {
+  OS << "\t.module\tginv\n";
+}
+
+void MipsTargetAsmStreamer::emitDirectiveModuleNoGINV() {
+  OS << "\t.module\tnoginv\n";
+}
+
 // This part is for ELF object output.
 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
                                              const MCSubtargetInfo &STI)
     : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
   MCAssembler &MCA = getStreamer().getAssembler();
 
   // It's possible that MCObjectFileInfo isn't fully initialized at this point
   // due to an initialization order problem where LLVMTargetMachine creates the

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td

class POOL32A_MFTC0_FM_MMR6<string instr_asm, bits<5> funct, bits<6> opcode>
   let Inst{25-21} = rt;
   let Inst{20-16} = rs;
   let Inst{15-14} = 0;
   let Inst{13-11} = sel;
   let Inst{10-6}  = funct;
   let Inst{5-0}   = opcode;
 }
 
+class POOL32A_GINV_FM_MMR6<string instr_asm, bits<2> ginv>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
+  bits<5> rs;
+  bits<2> type;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x0;
+  let Inst{25-21} = 0x0;
+  let Inst{20-16} = rs;
+  let Inst{15-13} = 0b011;
+  let Inst{12-11} = ginv;
+  let Inst{10-9}  = type;
+  let Inst{8-6}   = 0b101;
+  let Inst{5-0}   = 0b111100;
+}
+
 class POOL32F_MFTC1_FM_MMR6<string instr_asm, bits<8> funct>
     : MMR6Arch<instr_asm> {
   bits<5> rt;
   bits<5> fs;
 
   bits<32> Inst;
 
   let Inst{31-26} = 0b010101;

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
 class EI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"ei", 0x15d>;
 class DI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"di", 0b0100011101>;
 class ERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0x3cd>;
 class DERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0b1110001101>;
 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
+class GINVI_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvi", 0b00>;
+class GINVT_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvt", 0b10>;
 class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
 class LWP_MMR6_ENC : POOL32B_LWP_SWP_FM_MMR6<0x1>;
 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
class SDC2_SWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
   InstrItinClass Itinerary = itin;
   string BaseOpcode = opstr;
   bit mayStore = 1;
   string DecoderMethod = "DecodeFMemCop2MMR6";
 }
 class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2", II_SDC2>;
 class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2", II_SWC2>;
 
+class GINV_MMR6_DESC_BASE<string opstr,
+                          RegisterOperand SrcRC, InstrItinClass Itin> {
+  dag InOperandList = (ins SrcRC:$rs, uimm2:$type);
+  dag OutOperandList = (outs);
+  string AsmString = !strconcat(opstr, "\t$rs, $type");
+  list<dag> Pattern = [];
+  Format f = FrmFR;
+  string BaseOpcode = opstr;
+  InstrItinClass Itinerary = Itin;
+}
+
+class GINVI_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvi", GPR32Opnd,
+                                            II_GINVI> {
+  dag InOperandList = (ins GPR32Opnd:$rs);
+  string AsmString = "ginvi\t$rs";
+}
+class GINVT_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvt", GPR32Opnd,
+                                            II_GINVT>;
+
 /// Floating Point Instructions
 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
                             InstrItinClass Itin, bit isComm,
                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
   dag OutOperandList = (outs RC:$fd);
   dag InOperandList = (ins RC:$ft, RC:$fs);
   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];

 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
 def DI_MMR6 : StdMMR6Rel, DI_MMR6_DESC, DI_MMR6_ENC, ISA_MICROMIPS32R6;
 def ERET_MMR6 : StdMMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
 def DERET_MMR6 : StdMMR6Rel, DERET_MMR6_DESC, DERET_MMR6_ENC, ISA_MICROMIPS32R6;
 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
                   ISA_MICROMIPS32R6;
+def GINVI_MMR6 : R6MMR6Rel, GINVI_MMR6_ENC, GINVI_MMR6_DESC,
+                 ISA_MICROMIPS32R6, ASE_GINV;
+def GINVT_MMR6 : R6MMR6Rel, GINVT_MMR6_ENC, GINVT_MMR6_DESC,
+                 ISA_MICROMIPS32R6, ASE_GINV;
 def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
                    ISA_MICROMIPS32R6;
 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
                       ISA_MICROMIPS32R6;
 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;

llvm/trunk/lib/Target/Mips/Mips.td

 
 def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;
 
 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Mips R6 CRC ASE">;
 
 def FeatureVirt : SubtargetFeature<"virt", "HasVirt", "true",
                                    "Mips Virtualization ASE">;
 
+def FeatureGINV : SubtargetFeature<"ginv", "HasGINV", "true",
+                                   "Mips Global Invalidate ASE">;
+
 def FeatureMicroMips  : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
                                          "microMips mode">;
 
 def FeatureCnMips     : SubtargetFeature<"cnmips", "HasCnMips",
                                 "true", "Octeon cnMIPS Support",
                                 [FeatureMips64r2]>;
 
 def FeatureUseTCCInDIV : SubtargetFeature<

llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td

class SPECIAL3_2R_SZ_CRC<bits<2> sz, bits<3> direction> : MipsR6Inst {
   let Inst{20-16} = rt;
   let Inst{15-11} = 0b00000;
   let Inst{10-8} = direction;
   let Inst{7-6} = sz;
   let Inst{5-0} = 0b001111;
 
   string DecoderMethod = "DecodeCRC";
 }
+
+class SPECIAL3_GINV<bits<2> ginv> : MipsR6Inst {
+  bits<5> rs;
+  bits<2> type_;
+
+  let Inst{31-26} = OPGROUP_SPECIAL3.Value;
+  let Inst{25-21} = rs;
+  let Inst{20-10} = 0x0;
+  let Inst{9-8}   = type_;
+  let Inst{7-6}   = ginv;
+  let Inst{5-0}   = 0b111101;
+}

llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td

 
 class CRC32B_ENC  : SPECIAL3_2R_SZ_CRC<0,0>;
 class CRC32H_ENC  : SPECIAL3_2R_SZ_CRC<1,0>;
 class CRC32W_ENC  : SPECIAL3_2R_SZ_CRC<2,0>;
 class CRC32CB_ENC : SPECIAL3_2R_SZ_CRC<0,1>;
 class CRC32CH_ENC : SPECIAL3_2R_SZ_CRC<1,1>;
 class CRC32CW_ENC : SPECIAL3_2R_SZ_CRC<2,1>;
 
+class GINVI_ENC : SPECIAL3_GINV<0>;
+class GINVT_ENC : SPECIAL3_GINV<2>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Multiclasses
 //
 //===----------------------------------------------------------------------===//
 
 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
                           RegisterOperand FGROpnd,

 
 class CRC32B_DESC : CRC_DESC_BASE<"crc32b", GPR32Opnd, II_CRC32B>;
 class CRC32H_DESC : CRC_DESC_BASE<"crc32h", GPR32Opnd, II_CRC32H>;
 class CRC32W_DESC : CRC_DESC_BASE<"crc32w", GPR32Opnd, II_CRC32W>;
 class CRC32CB_DESC : CRC_DESC_BASE<"crc32cb", GPR32Opnd, II_CRC32CB>;
 class CRC32CH_DESC : CRC_DESC_BASE<"crc32ch", GPR32Opnd, II_CRC32CH>;
 class CRC32CW_DESC : CRC_DESC_BASE<"crc32cw", GPR32Opnd, II_CRC32CW>;
 
+class GINV_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+                     InstrItinClass itin> : MipsR6Arch<instr_asm> {
+  dag OutOperandList = (outs);
+  dag InOperandList = (ins GPROpnd:$rs, uimm2:$type_);
+  string AsmString = !strconcat(instr_asm, "\t$rs, $type_");
+  list<dag> Pattern = [];
+  InstrItinClass Itinerary = itin;
+  bit hasSideEffects = 1;
+}
+
+class GINVI_DESC : GINV_DESC_BASE<"ginvi", GPR32Opnd, II_GINVI> {
+  dag InOperandList = (ins GPR32Opnd:$rs);
+  string AsmString = "ginvi\t$rs";
+}
+class GINVT_DESC : GINV_DESC_BASE<"ginvt", GPR32Opnd, II_GINVT>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
 def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
   def CRC32B : R6MMR6Rel, CRC32B_ENC, CRC32B_DESC, ISA_MIPS32R6, ASE_CRC;
   def CRC32H : R6MMR6Rel, CRC32H_ENC, CRC32H_DESC, ISA_MIPS32R6, ASE_CRC;
   def CRC32W : R6MMR6Rel, CRC32W_ENC, CRC32W_DESC, ISA_MIPS32R6, ASE_CRC;
   def CRC32CB : R6MMR6Rel, CRC32CB_ENC, CRC32CB_DESC, ISA_MIPS32R6, ASE_CRC;
   def CRC32CH : R6MMR6Rel, CRC32CH_ENC, CRC32CH_DESC, ISA_MIPS32R6, ASE_CRC;
   def CRC32CW : R6MMR6Rel, CRC32CW_ENC, CRC32CW_DESC, ISA_MIPS32R6, ASE_CRC;
 }
 
+let AdditionalPredicates = [NotInMicroMips] in {
+  def GINVI : R6MMR6Rel, GINVI_ENC, GINVI_DESC, ISA_MIPS32R6, ASE_GINV;
+  def GINVT : R6MMR6Rel, GINVT_ENC, GINVT_DESC, ISA_MIPS32R6, ASE_GINV;
+}
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Aliases
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsInstAlias<"dvp", (DVP ZERO), 0>, ISA_MIPS32R6;
 def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6;

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

 def UseIndirectJumpsHazard : Predicate<"Subtarget->useIndirectJumpsHazard()">,
                             AssemblerPredicate<"FeatureUseIndirectJumpsHazard">;
 def NoIndirectJumpGuards : Predicate<"!Subtarget->useIndirectJumpsHazard()">,
                            AssemblerPredicate<"!FeatureUseIndirectJumpsHazard">;
 def HasCRC   : Predicate<"Subtarget->hasCRC()">,
                AssemblerPredicate<"FeatureCRC">;
 def HasVirt  : Predicate<"Subtarget->hasVirt()">,
                AssemblerPredicate<"FeatureVirt">;
+def HasGINV  : Predicate<"Subtarget->hasGINV()">,
+               AssemblerPredicate<"FeatureGINV">;
 // TODO: Add support for FPOpFusion::Standard
 def AllowFPOpFusion : Predicate<"TM.Options.AllowFPOpFusion =="
                                 " FPOpFusion::Fast">;
 //===----------------------------------------------------------------------===//
 // Mips GPR size adjectives.
 // They are mutually exclusive.
 //===----------------------------------------------------------------------===//
 

 class ASE_CRC {
   list <Predicate> ASEPredicate = [HasCRC];
 }
 
 class ASE_VIRT {
   list <Predicate> ASEPredicate = [HasVirt];
 }
 
+class ASE_GINV {
+  list <Predicate> ASEPredicate = [HasGINV];
+}
+
 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
 // It can be used only on instructions that doesn't inherit PredicateControl.
 class ISA_MICROMIPS_NOT_32R6 : PredicateControl {
   let InsnPredicates = [NotMips32r6];
   let EncodingPredicates = [InMicroMips];
 }
 
 class ASE_NOT_DSP {

llvm/trunk/lib/Target/Mips/MipsSchedule.td

 def II_DSUBU            : InstrItinClass;
 def II_DSUB             : InstrItinClass;
 def II_DVPE             : InstrItinClass;
 def II_EMT              : InstrItinClass;
 def II_EVPE             : InstrItinClass;
 def II_EXT              : InstrItinClass; // Any EXT instruction
 def II_FLOOR            : InstrItinClass;
 def II_FORK             : InstrItinClass;
+def II_GINVI            : InstrItinClass;
+def II_GINVT            : InstrItinClass;
 def II_HYPCALL          : InstrItinClass;
 def II_INS              : InstrItinClass; // Any INS instruction
 def II_IndirectBranchPseudo : InstrItinClass; // Indirect branch pseudo.
 def II_J                : InstrItinClass;
 def II_JAL              : InstrItinClass;
 def II_JALR             : InstrItinClass;
 def II_JALR_HB          : InstrItinClass;
 def II_JALRC            : InstrItinClass;
def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
   InstrItinData<II_HYPCALL         , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_TLBGINV         , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_TLBGINVF        , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_TLBGP           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_TLBGR           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_TLBWI           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_TLBWR           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_DMFGC0          , [InstrStage<2,  [ALU]>]>,
-  InstrItinData<II_DMTGC0          , [InstrStage<2,  [ALU]>]>
+  InstrItinData<II_DMTGC0          , [InstrStage<2,  [ALU]>]>,
+  InstrItinData<II_GINVI           , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_GINVT           , [InstrStage<1,  [ALU]>]>
 ]>;

llvm/trunk/lib/Target/Mips/MipsSubtarget.h

class MipsSubtarget : public MipsGenSubtargetInfo {
   bool HasMT;
 
   // HasCRC -- supports R6 CRC ASE
   bool HasCRC;
 
   // HasVirt -- supports Virtualization ASE
   bool HasVirt;
 
+  // HasGINV -- supports R6 Global INValidate ASE
+  bool HasGINV;
+
   // Use hazard variants of the jump register instructions for indirect
   // function calls and jump tables.
   bool UseIndirectJumpsHazard;
 
   // Disable use of the `jal` instruction.
   bool UseLongCalls = false;
 
   /// The minimum alignment known to hold of the stack frame on
public:
   bool hasDSPR2() const { return HasDSPR2; }
   bool hasDSPR3() const { return HasDSPR3; }
   bool hasMSA() const { return HasMSA; }
   bool disableMadd4() const { return DisableMadd4; }
   bool hasEVA() const { return HasEVA; }
   bool hasMT() const { return HasMT; }
   bool hasCRC() const { return HasCRC; }
   bool hasVirt() const { return HasVirt; }
+  bool hasGINV() const { return HasGINV; }
   bool useIndirectJumpsHazard() const {
     return UseIndirectJumpsHazard && hasMips32r2();
   }
   bool useSmallSection() const { return UseSmallSection; }
 
   bool hasStandardEncoding() const { return !inMips16Mode(); }
 
   bool useSoftFloat() const { return IsSoftFloat; }

llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp

: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
       NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
       IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
       HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
       HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
       InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
       HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
       Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
       HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
-      HasVirt(false), UseIndirectJumpsHazard(false),
+      HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false),
       StackAlignOverride(StackAlignOverride),
       TM(TM), TargetTriple(TT), TSInfo(),
       InstrInfo(
           MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
       FrameLowering(MipsFrameLowering::create(*this)),
       TLInfo(MipsTargetLowering::create(TM, *this)) {
 
   if (MipsArchVersion == MipsDefault)

llvm/trunk/lib/Target/Mips/MipsTargetStreamer.h

public:
   virtual void emitDirectiveSetMsa();
   virtual void emitDirectiveSetNoMsa();
   virtual void emitDirectiveSetMt();
   virtual void emitDirectiveSetNoMt();
   virtual void emitDirectiveSetCRC();
   virtual void emitDirectiveSetNoCRC();
   virtual void emitDirectiveSetVirt();
   virtual void emitDirectiveSetNoVirt();
+  virtual void emitDirectiveSetGINV();
+  virtual void emitDirectiveSetNoGINV();
   virtual void emitDirectiveSetAt();
   virtual void emitDirectiveSetAtWithArg(unsigned RegNo);
   virtual void emitDirectiveSetNoAt();
   virtual void emitDirectiveEnd(StringRef Name);
 
   virtual void emitDirectiveEnt(const MCSymbol &Symbol);
   virtual void emitDirectiveAbiCalls();
   virtual void emitDirectiveNaN2008();
public:
   virtual void emitDirectiveModuleMT();
   virtual void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value);
   virtual void emitDirectiveSetOddSPReg();
   virtual void emitDirectiveSetNoOddSPReg();
   virtual void emitDirectiveModuleCRC();
   virtual void emitDirectiveModuleNoCRC();
   virtual void emitDirectiveModuleVirt();
   virtual void emitDirectiveModuleNoVirt();
+  virtual void emitDirectiveModuleGINV();
+  virtual void emitDirectiveModuleNoGINV();
 
   void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
              const MCSubtargetInfo *STI);
   void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
               const MCSubtargetInfo *STI);
   void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
               const MCSubtargetInfo *STI);
   void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
public:
   void emitDirectiveSetMsa() override;
   void emitDirectiveSetNoMsa() override;
   void emitDirectiveSetMt() override;
   void emitDirectiveSetNoMt() override;
   void emitDirectiveSetCRC() override;
   void emitDirectiveSetNoCRC() override;
   void emitDirectiveSetVirt() override;
   void emitDirectiveSetNoVirt() override;
+  void emitDirectiveSetGINV() override;
+  void emitDirectiveSetNoGINV() override;
   void emitDirectiveSetAt() override;
   void emitDirectiveSetAtWithArg(unsigned RegNo) override;
   void emitDirectiveSetNoAt() override;
   void emitDirectiveEnd(StringRef Name) override;
 
   void emitDirectiveEnt(const MCSymbol &Symbol) override;
   void emitDirectiveAbiCalls() override;
   void emitDirectiveNaN2008() override;
public:
   void emitDirectiveModuleOddSPReg() override;
   void emitDirectiveModuleSoftFloat() override;
   void emitDirectiveModuleHardFloat() override;
   void emitDirectiveModuleMT() override;
   void emitDirectiveModuleCRC() override;
   void emitDirectiveModuleNoCRC() override;
   void emitDirectiveModuleVirt() override;
   void emitDirectiveModuleNoVirt() override;
+  void emitDirectiveModuleGINV() override;
+  void emitDirectiveModuleNoGINV() override;
   void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value) override;
   void emitDirectiveSetOddSPReg() override;
   void emitDirectiveSetNoOddSPReg() override;
 };
 
 // This part is for ELF object output
 class MipsTargetELFStreamer : public MipsTargetStreamer {
   bool MicroMipsEnabled;

llvm/trunk/test/MC/Disassembler/Mips/ginv/valid-el.txt

+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux-gnu \
+# RUN:   -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
+
+0x3d 0x02 0x40 0x7c  # CHECK: ginvi $2
+0xbd 0x02 0x40 0x7c  # CHECK: ginvt $2, 2

llvm/trunk/test/MC/Disassembler/Mips/ginv/valid-micromips-el.txt

+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux-gnu \
+# RUN:   -mcpu=mips32r6 -mattr=+micromips,+ginv | FileCheck %s
+
+0x02 0x00 0x7c 0x65  # CHECK: ginvi $2
+0x02 0x00 0x7c 0x75  # CHECK: ginvt $2, 2

llvm/trunk/test/MC/Disassembler/Mips/ginv/valid-micromips.txt

+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux-gnu \
+# RUN:   -mcpu=mips32r6 -mattr=+micromips,+ginv | FileCheck %s
+
+0x00 0x02 0x65 0x7c  # CHECK: ginvi $2
+0x00 0x02 0x75 0x7c  # CHECK: ginvt $2, 2

llvm/trunk/test/MC/Disassembler/Mips/ginv/valid.txt

+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux-gnu \
+# RUN:   -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
+
+0x7c 0x40 0x02 0x3d  # CHECK: ginvi $2
+0x7c 0x40 0x02 0xbd  # CHECK: ginvt $2, 2

llvm/trunk/test/MC/Mips/ginv/invalid.s

+# Instructions that are invalid.
+#
+# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+ginv 2>%t1
+# RUN: FileCheck %s < %t1
+# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 -mattr=+ginv 2>%t1
+# RUN: FileCheck %s < %t1
+# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 \
+# RUN:     -mattr=+micromips,+ginv 2>%t1
+# RUN: FileCheck %s < %t1
+
+  ginvi            # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  ginvi 0          # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+  ginvi $4, 0      # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+  ginvi $4, $5     # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+  ginvi 0($4)      # CHECK: :[[@LINE]]:10: error: unexpected token in argument list
+  ginvt            # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  ginvt 0          # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+  ginvt $4         # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  ginvt $4, $5     # CHECK: :[[@LINE]]:13: error: expected 2-bit unsigned immediate
+  ginvt $4, 4      # CHECK: :[[@LINE]]:13: error: expected 2-bit unsigned immediate
+  ginvt $4, -1     # CHECK: :[[@LINE]]:13: error: expected 2-bit unsigned immediate
+  ginvt $4, 0, 1   # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+  ginvt $4, 0($4)  # CHECK: :[[@LINE]]:14: error: invalid operand for instruction

llvm/trunk/test/MC/Mips/ginv/module-ginv.s

+# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -mcpu=mips32r6 | \
+# RUN:   FileCheck %s -check-prefix=CHECK-ASM
+#
+# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -mcpu=mips32r6 \
+# RUN:   -filetype=obj -o - | \
+# RUN:   llvm-readobj -mips-abi-flags - | \
+# RUN:   FileCheck %s -check-prefix=CHECK-OBJ
+
+# CHECK-ASM: .module ginv
+
+# Check if the MIPS.abiflags section was correctly emitted:
+# CHECK-OBJ: MIPS ABI Flags {
+# CHECK-OBJ:   ASEs [ (0x20000)
+# CHECK-OBJ:     GINV (0x20000)
+# CHECK-OBJ: }
+
+  .module ginv
+  ginvi $4
+
+# FIXME: Test should include gnu_attributes directive when implemented.
+#        An explicit .gnu_attribute must be checked against the effective
+#        command line options and any inconsistencies reported via a warning.

llvm/trunk/test/MC/Mips/ginv/module-noginv.s

+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+ginv | \
+# RUN:   FileCheck %s -check-prefix=CHECK-ASM
+#
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -filetype=obj -o - -mattr=+ginv | \
+# RUN:   llvm-readobj -mips-abi-flags - | \
+# RUN:   FileCheck %s -check-prefix=CHECK-OBJ
+
+# CHECK-ASM: .module noginv
+
+# Check that MIPS.abiflags has no GINV flag.
+# CHECK-OBJ: MIPS ABI Flags {
+# CHECK-OBJ:   ASEs [ (0x0)
+# CHECK-OBJ-NOT:   ASEs [ (0x20000)
+# CHECK-OBJ-NOT:     GINV (0x20000)
+# CHECK-OBJ: }
+
+  .module noginv
+
+# FIXME: Test should include gnu_attributes directive when implemented.
+#        An explicit .gnu_attribute must be checked against the effective
+#        command line options and any inconsistencies reported via a warning.

llvm/trunk/test/MC/Mips/ginv/set-ginv-directive.s

+# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -show-encoding \
+# RUN:   -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux-gnu -show-encoding \
+# RUN:   -mcpu=mips64r6 -mattr=+ginv | FileCheck %s
+
+  .set ginv
+  ginvi $4  # CHECK: ginvi $4  # encoding: [0x7c,0x80,0x00,0x3d]

llvm/trunk/test/MC/Mips/ginv/set-noginv-directive.s

+# RUN: not llvm-mc %s -triple=mips-unknown-linux-gnu -show-encoding \
+# RUN:     -mcpu=mips32r6 -mattr=+ginv 2>%t1
+# RUN: FileCheck %s < %t1
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux-gnu -show-encoding \
+# RUN:     -mcpu=mips64r6 -mattr=+ginv 2>%t1
+# RUN: FileCheck %s < %t1
+
+  .set noginv
+  ginvi $4, 2  # CHECK: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/ginv/valid-micromips.s

+# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -show-encoding \
+# RUN:   -mcpu=mips32r6 -mattr=+micromips,+ginv | FileCheck %s
+
+  ginvi $4           # CHECK: ginvi $4         # encoding: [0x00,0x04,0x61,0x7c]
+  ginvt $4, 2        # CHECK: ginvt $4, 2      # encoding: [0x00,0x04,0x75,0x7c]

llvm/trunk/test/MC/Mips/ginv/valid.s

+# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -show-encoding \
+# RUN:   -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux-gnu -show-encoding \
+# RUN:   -mcpu=mips64r6 -mattr=+ginv | FileCheck %s
+
+  ginvi $4           # CHECK: ginvi $4         # encoding: [0x7c,0x80,0x00,0x3d]
+  ginvt $4, 2        # CHECK: ginvt $4, 2      # encoding: [0x7c,0x80,0x02,0xbd]

llvm/trunk/tools/llvm-readobj/ELFDumper.cpp

static const EnumEntry<unsigned> ElfMipsASEFlags[] = {
   {"MT",                 Mips::AFL_ASE_MT},
   {"SmartMIPS",          Mips::AFL_ASE_SMARTMIPS},
   {"VZ",                 Mips::AFL_ASE_VIRT},
   {"MSA",                Mips::AFL_ASE_MSA},
   {"MIPS16",             Mips::AFL_ASE_MIPS16},
   {"microMIPS",          Mips::AFL_ASE_MICROMIPS},
   {"XPA",                Mips::AFL_ASE_XPA},
   {"CRC",                Mips::AFL_ASE_CRC},
+  {"GINV",               Mips::AFL_ASE_GINV},
 };
 
 static const EnumEntry<unsigned> ElfMipsFpABIType[] = {
   {"Hard or soft float",                  Mips::Val_GNU_MIPS_ABI_FP_ANY},
   {"Hard float (double precision)",       Mips::Val_GNU_MIPS_ABI_FP_DOUBLE},
   {"Hard float (single precision)",       Mips::Val_GNU_MIPS_ABI_FP_SINGLE},
   {"Soft float",                          Mips::Val_GNU_MIPS_ABI_FP_SOFT},
   {"Hard float (MIPS32r2 64-bit FPU 12 callee-saved)",