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Differential D46125

[mips] Correct clo/clz predicates
ClosedPublic

Authored by sdardis on Apr 26 2018, 8:00 AM.

Details

Reviewers
smaksimovic
abeserminji
atanasyan
Commits
rG7563624fcba4: [mips] Correct clo/clz predicates
rL331754: [mips] Correct clo/clz predicates

Diff Detail

Repository
rL LLVM

Event Timeline

sdardis created this revision.Apr 26 2018, 8:00 AM
Herald added a subscriber: arichardson. · View Herald TranscriptApr 26 2018, 8:00 AM
sdardis added a comment.May 3 2018, 2:23 AM

Ping.

atanasyan accepted this revision.May 3 2018, 4:01 AM

LGTM

This revision is now accepted and ready to land.May 3 2018, 4:01 AM
Closed by commit rL331754: [mips] Correct clo/clz predicates (authored by sdardis). · Explain WhyMay 8 2018, 2:54 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
4 lines
35 lines
test/
MC/
Mips/
micromips/
2 lines
mips32/
2 lines
mips32r2/
2 lines
mips32r3/
2 lines
mips32r5/
2 lines
mips32r6/
2 lines

Diff 145657

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 915 Lines • ▼ Show 20 Lineslet DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
/// Multiply Add/Sub Instructions /// Multiply Add/Sub Instructions
def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>; def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>; def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>; def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>; def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
/// Count Leading /// Count Leading
def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>, def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>,
ISA_MIPS32; ISA_MICROMIPS;
def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>, def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>,
ISA_MIPS32; ISA_MICROMIPS;
/// Sign Ext In Register Instructions. /// Sign Ext In Register Instructions.
def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
SEB_FM_MM<0x0ac>, ISA_MICROMIPS; SEB_FM_MM<0x0ac>, ISA_MICROMIPS;
def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
SEB_FM_MM<0x0ec>, ISA_MICROMIPS; SEB_FM_MM<0x0ec>, ISA_MICROMIPS;
/// Word Swap Bytes Within Halfwords /// Word Swap Bytes Within Halfwords
▲ Show 20 Lines • Show All 416 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 2,273 Lines • ▼ Show 20 Lines def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6; MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>, def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6; MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
} }
def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>, def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>, def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug let AdditionalPredicates = [NotInMicroMips] in {
AdditionalPredicates = [NotInMicroMips] in {
def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>, def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>, def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
/// Sign Ext In Register Instructions. /// Sign Ext In Register Instructions.
def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
SEB_FM<0x10, 0x20>, ISA_MIPS32R2; SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
SEB_FM<0x18, 0x20>, ISA_MIPS32R2; SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
}
/// Count Leading /// Count Leading
def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>, def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>,
ISA_MIPS32_NOT_32R6_64R6; ISA_MIPS32_NOT_32R6_64R6;
def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>, def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>,
ISA_MIPS32_NOT_32R6_64R6; ISA_MIPS32_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in {
/// Word Swap Bytes Within Halfwords /// Word Swap Bytes Within Halfwords
def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>, def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>,
ISA_MIPS32R2; ISA_MIPS32R2;
} }
/// No operation. /// No operation.
def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
▲ Show 20 Lines • Show All 887 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/micromips/valid.s

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Linesmthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x54,0x80,0x38,0x3b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D32_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D32_MM
madd $4, $5 # CHECK: madd $4, $5 # encoding: [0x00,0xa4,0xcb,0x3c] madd $4, $5 # CHECK: madd $4, $5 # encoding: [0x00,0xa4,0xcb,0x3c]
maddu $4, $5 # CHECK: maddu $4, $5 # encoding: [0x00,0xa4,0xdb,0x3c] maddu $4, $5 # CHECK: maddu $4, $5 # encoding: [0x00,0xa4,0xdb,0x3c]
msub $4, $5 # CHECK: msub $4, $5 # encoding: [0x00,0xa4,0xeb,0x3c] msub $4, $5 # CHECK: msub $4, $5 # encoding: [0x00,0xa4,0xeb,0x3c]
msubu $4, $5 # CHECK: msubu $4, $5 # encoding: [0x00,0xa4,0xfb,0x3c] msubu $4, $5 # CHECK: msubu $4, $5 # encoding: [0x00,0xa4,0xfb,0x3c]
neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x54,0x02,0x2b,0x7b] neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x54,0x02,0x2b,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D32_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D32_MM
clz $9, $6 # CHECK: clz $9, $6 # encoding: [0x01,0x26,0x5b,0x3c] clz $9, $6 # CHECK: clz $9, $6 # encoding: [0x01,0x26,0x5b,0x3c]
# CHECK-NEXT: # <MCInst #{{.*}} CLZ_MM
clo $9, $6 # CHECK: clo $9, $6 # encoding: [0x01,0x26,0x4b,0x3c] clo $9, $6 # CHECK: clo $9, $6 # encoding: [0x01,0x26,0x4b,0x3c]
# CHECK-NEXT: # <MCInst #{{.*}} CLO_MM
seb $9, $6 # CHECK: seb $9, $6 # encoding: [0x01,0x26,0x2b,0x3c] seb $9, $6 # CHECK: seb $9, $6 # encoding: [0x01,0x26,0x2b,0x3c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SEB_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} SEB_MM
seb $9 # CHECK: seb $9, $9 # encoding: [0x01,0x29,0x2b,0x3c] seb $9 # CHECK: seb $9, $9 # encoding: [0x01,0x29,0x2b,0x3c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SEB_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} SEB_MM
seh $9, $6 # CHECK: seh $9, $6 # encoding: [0x01,0x26,0x3b,0x3c] seh $9, $6 # CHECK: seh $9, $6 # encoding: [0x01,0x26,0x3b,0x3c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SEH_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} SEH_MM
seh $9 # CHECK: seh $9, $9 # encoding: [0x01,0x29,0x3b,0x3c] seh $9 # CHECK: seh $9, $9 # encoding: [0x01,0x29,0x3b,0x3c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SEH_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} SEH_MM
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llvm/trunk/test/MC/Mips/mips32/valid.s

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Linesa:
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
# CHECK-NEXT: # <MCInst #{{.*}} CLO
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
# CHECK-NEXT: # <MCInst #{{.*}} CLZ
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21] cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S
cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21] cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W
cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20] cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D32 # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D32
cvt.s.w $f22,$f15 cvt.s.w $f22,$f15
▲ Show 20 Lines • Show All 242 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r2/valid.s

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Linesa:
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
# CHECK-NEXT: # <MCInst #{{.*}} CLO
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
# CHECK-NEXT: # <MCInst #{{.*}} CLZ
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21] cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S
cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21] cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W
cvt.l.d $f24,$f15 cvt.l.d $f24,$f15
cvt.l.s $f11,$f29 cvt.l.s $f11,$f29
cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20] cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
▲ Show 20 Lines • Show All 295 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r3/valid.s

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Linesa:
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
# CHECK-NEXT: # <MCInst #{{.*}} CLO
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
# CHECK-NEXT: # <MCInst #{{.*}} CLZ
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21] cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S
cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21] cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W
cvt.l.d $f24,$f15 cvt.l.d $f24,$f15
cvt.l.s $f11,$f29 cvt.l.s $f11,$f29
cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20] cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
▲ Show 20 Lines • Show All 298 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r5/valid.s

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Linesa:
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
# CHECK-NEXT: # <MCInst #{{.*}} CLO
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
# CHECK-NEXT: # <MCInst #{{.*}} CLZ
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21] cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S
cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21] cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W
cvt.l.d $f24,$f15 cvt.l.d $f24,$f15
cvt.l.s $f11,$f29 cvt.l.s $f11,$f29
cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20] cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
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llvm/trunk/test/MC/Mips/mips32r6/valid.s

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jic $12, -3920 # CHECK: jic $12, -3920 # encoding: [0xd8,0x0c,0xf0,0xb0] jic $12, -3920 # CHECK: jic $12, -3920 # encoding: [0xd8,0x0c,0xf0,0xb0]
ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43] ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43]
lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7] lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7]
sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75] sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75]
swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30] swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30]
ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6] ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6]
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51]
# CHECK-NEXT: # <MCInst #{{.*}} CLO
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
# CHECK-NEXT: # <MCInst #{{.*}} CLZ
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16] rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96] rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20] seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20] seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20] seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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