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[ARM] Enable misched for R52.
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Authored by dmgreen on Apr 26 2018, 3:00 AM.

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Reviewers

javed.absar
fhahn
samparker
MatzeB

Summary

Back when the R52 schedule was added in rL286949, there was no way
to enable machine schedules in ARM for specific cores. Since then a
target feature has been added. This enables the feature for R52, removing
the need manually specify compiler flags.

Diff Detail

Event Timeline

dmgreen created this revision.Apr 26 2018, 3:00 AM

Herald added subscribers: chrib, kristof.beyls. · View Herald TranscriptApr 26 2018, 3:00 AM

LGTM, assuming you are happy with the perf numbers.

I think it is great to see some Arm cores moving to the MachineScheduler.

This revision is now accepted and ready to land.Apr 26 2018, 3:31 AM

Thanks. The perf numbers are indeed looking good.

rL331027

Revision Contents

Path

Size

lib/

Target/

ARM/

ARM.td

1 line

test/

CodeGen/

ARM/

cortexr52-misched-basic.ll

2 lines

Diff 144087

lib/Target/ARM/ARM.td

	Show First 20 Lines • Show All 993 Lines • ▼ Show 20 Lines

	def : ProcNoItin<"kryo", [ARMv8a, ProcKryo,			def : ProcNoItin<"kryo", [ARMv8a, ProcKryo,
	FeatureHWDivThumb,			FeatureHWDivThumb,
	FeatureHWDivARM,			FeatureHWDivARM,
	FeatureCrypto,			FeatureCrypto,
	FeatureCRC]>;			FeatureCRC]>;

	def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,			def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,
				FeatureUseMISched,
	FeatureFPAO]>;			FeatureFPAO]>;

	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//
	// Register File Description			// Register File Description
	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//

	include "ARMRegisterInfo.td"			include "ARMRegisterInfo.td"
	include "ARMRegisterBanks.td"			include "ARMRegisterBanks.td"
	Show All 38 Lines

test/CodeGen/ARM/cortexr52-misched-basic.ll

	; REQUIRES: asserts			; REQUIRES: asserts
	; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null \| FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED			; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null \| FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED
	; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null \| FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC			; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null \| FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
	;			;
	; Check the latency for instructions for both generic and cortex-r52.			; Check the latency for instructions for both generic and cortex-r52.
	; Cortex-r52 machine model will cause the div to be sceduled before eor			; Cortex-r52 machine model will cause the div to be sceduled before eor
	; as div takes more cycles to compute than eor.			; as div takes more cycles to compute than eor.
	;			;
	; CHECK: ******** MI Scheduling ********			; CHECK: ******** MI Scheduling ********
	; CHECK: foo:%bb.0 entry			; CHECK: foo:%bb.0 entry
	Show All 29 Lines