[MIR] Reset unique MBB numbering in MachineFunction::reset()

[rtereshin]

Summary

No need to waste space nor number MBBs differently if MF gets recreated.

[rtereshin]

test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir

56 ↗

(On Diff #143995)

pre-patch llc would re-number the basic block from 0 to 1 here.

llvm/trunk/lib/CodeGen/MachineFunction.cpp

 void MachineFunction::clear() {
   Properties.reset();
   // Don't call destructors on MachineInstr and MachineOperand. All of their
   // memory comes from the BumpPtrAllocator which is about to be purged.
   //
   // Do call MachineBasicBlock destructors, it contains std::vectors.
   for (iterator I = begin(), E = end(); I != E; I = BasicBlocks.erase(I))
     I->Insts.clearAndLeakNodesUnsafely();
+  MBBNumbering.clear();
 
   InstructionRecycler.clear(Allocator);
   OperandRecycler.clear(Allocator);
   BasicBlockRecycler.clear(Allocator);
   CodeViewAnnotations.clear();
   VariableDbgInfos.clear();
   if (RegInfo) {
     RegInfo->~MachineRegisterInfo();

llvm/trunk/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir

 # RUN: llc -mtriple aarch64-- -run-pass instruction-select -simplify-mir \
 # RUN:     -verify-machineinstrs %s -o - | FileCheck %s
 #
 # RUN: llc -mtriple aarch64-- -global-isel=true -global-isel-abort=2 \
 # RUN:     -start-after=regbankselect -stop-before=expand-isel-pseudos \
 # RUN:     -simplify-mir -verify-machineinstrs %s -o - 2>&1 \
 # RUN:    | FileCheck %s --check-prefix=FALLBACK
 
 # Test that:
 # 1) MIRParser can deserialize FailedISel property.
 # 2) Machine Verifier respects FailedISel and doesn't complain needlessly.
 # 3) MIRPrinter is able to print FailedISel MIR after InstructionSelect pass.
 # 4) MIRPrinter can serialize FailedISel property.
 # 5) It's possible to start llc mid-GlobalISel pipeline from a MIR file with
 #    the FailedISel property set to true and watch it properly fallback to
 #    FastISel / SelectionDAG ISel.
+# 6) Resetting a MachineFunction resets unique MachineBasicBlock IDs as well.
 --- |
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64--"
 
   define i32 @test(i32 %a, i32 %b) #0 {
   entry:
     %add = add i32 %b, %a
     ret i32 %add

 # FALLBACK-NOT: failedISel
 name:            test
 alignment:       2
 legalized:       true
 regBankSelected: true
 failedISel:      true
 tracksRegLiveness: true
 body:             |
-  bb.1.entry:
+  bb.0.entry:
     liveins: $w0, $w1
 
     ; CHECK: liveins: $w0, $w1
+    ;
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY1]], [[COPY]]
     ; CHECK: $w0 = COPY [[ADD]](s32)
     ; CHECK: RET_ReallyLR implicit $w0
     ;
-    ; FALLBACK: liveins: $w0, $w1
+    ; FALLBACK: body: |
+    ; FALLBACK-NEXT: bb.0.entry:
+    ; FALLBACK-NEXT: liveins: $w0, $w1
+    ;
     ; FALLBACK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
     ; FALLBACK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
     ; FALLBACK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
     ; FALLBACK: $w0 = COPY [[ADDWrr]]
     ; FALLBACK: RET_ReallyLR implicit $w0
 
     %0:_(s32) = COPY $w0
     %1:_(s32) = COPY $w1
     %2:gpr(s32) = G_ADD %1, %0
     $w0 = COPY %2(s32)
     RET_ReallyLR implicit $w0
 ...