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[AMDGPU][Waitcnt] Take ISA target into account for s_waitcnt expcnt instr generation
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Authored by msearles on Apr 25 2018, 8:51 AM.

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Summary

As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.

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Repository
rL LLVM

Event Timeline

msearles created this revision.Apr 25 2018, 8:51 AM
This revision is now accepted and ready to land.Apr 25 2018, 9:09 AM
t-tye accepted this revision.Apr 25 2018, 4:07 PM

LGTM

This revision was automatically updated to reflect the committed changes.