[X86] movdiri and movdir64b instructions

[craig.topper]

lib/Support/Host.cpp

1268

Drop the comment and put these bit checks with the other Leaf7 ECX bit checks above.

lib/Target/X86/X86InstrMovdir.td

1

I don't know that a new file is warranted for so few instructions. Just add them to X86InstrInfo.td

[craig.topper]

test/CodeGen/X86/movdir-intrinsic.ll

2

How about movdir-intrinsic-x86.ll

test/CodeGen/X86/movdirq-intrinsic.ll

2

How about movdir-intrinsic-x86_64.ll

[RKSimon]

lib/Target/X86/X86InstrInfo.td

2700

Please can you add scheduling classes

[RKSimon]

No more comments from me - @craig.topper are you happy with this?

[craig.topper]

LGTM

include/llvm/IR/IntrinsicsX86.td

 let TargetPrefix = "x86" in {
   def int_x86_umonitor : GCCBuiltin<"__builtin_ia32_umonitor">,
               Intrinsic<[], [llvm_ptr_ty], []>;
   def int_x86_umwait : GCCBuiltin<"__builtin_ia32_umwait">,
               Intrinsic<[llvm_i8_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
   def int_x86_tpause : GCCBuiltin<"__builtin_ia32_tpause">,
               Intrinsic<[llvm_i8_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 }
+
+//===----------------------------------------------------------------------===//
+// Direct Move Instructions
+
+let TargetPrefix = "x86" in {
+  def int_x86_directstore32 : GCCBuiltin<"__builtin_ia32_directstore_u32">,
+      Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], []>;
+  def int_x86_directstore64 : GCCBuiltin<"__builtin_ia32_directstore_u64">,
+      Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], []>;
+  def int_x86_movdir64b : GCCBuiltin<"__builtin_ia32_movdir64b">,
+      Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], []>;
+}

lib/Support/Host.cpp

bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
   Features["avx512vnni"]      = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
   Features["avx512bitalg"]    = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
   Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
   Features["rdpid"]           = HasLeaf7 && ((ECX >> 22) & 1);
   Features["cldemote"]        = HasLeaf7 && ((ECX >> 25) & 1);
 
   Features["ibt"] = HasLeaf7 && ((EDX >> 20) & 1);
 
+  // Direct move instruction support.
+  Features["movdiri"]         = HasLeaf7 && ((ECX >> 27) & 1);
+  Features["movdir64b"]       = HasLeaf7 && ((ECX >> 28) & 1);
+
   bool HasLeafD = MaxLevel >= 0xd &&
                   !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
 
   // Only enable XSAVE if OS has enabled support for saving YMM state.
   Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
   Features["xsavec"]   = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
   Features["xsaves"]   = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
 

lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp

if ((insn->vectorExtensionType == TYPE_EVEX &&
         insn->instructionID = instructionIDWithREXW;
         insn->spec = specifierForUID(instructionIDWithREXW);
         return 0;
       }
     }
   }
 
   /*
-   * Absolute moves and umonitor need special handling.
+   * Absolute moves, umonitor, and movdir64b need special handling.
    * -For 16-bit mode because the meaning of the AdSize and OpSize prefixes are
    *  inverted w.r.t.
    * -For 32-bit mode we need to ensure the ADSIZE prefix is observed in
    *  any position.
    */
   if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) ||
-      (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE))) {
+      (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) ||
+      (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8)) {
     /* Make sure we observed the prefixes in any position. */
     if (insn->hasAdSize)
       attrMask |= ATTR_ADSIZE;
     if (insn->hasOpSize)
       attrMask |= ATTR_OPSIZE;
 
     /* In 16-bit, invert the attributes. */
     if (insn->mode == MODE_16BIT) {
       attrMask ^= ATTR_ADSIZE;
+
       /* The OpSize attribute is only valid with the absolute moves. */
       if (insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0))
         attrMask ^= ATTR_OPSIZE;
     }
 
     if (getIDWithAttrMask(&instructionID, insn, attrMask))
       return -1;
 

lib/Target/X86/X86.td

 // to provide their own custom thunk definitions in highly specialized
 // environments such as a kernel that does boot-time hot patching.
 def FeatureRetpolineExternalThunk
     : SubtargetFeature<
           "retpoline-external-thunk", "UseRetpolineExternalThunk", "true",
           "Enable retpoline, but with an externally provided thunk.",
           [FeatureRetpoline]>;
 
+// Direct Move instructions.
+def FeatureMOVDIRI  : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
+                                       "Support movdiri instruction">;
+def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",
+                                        "Support movdir64b instruction">;
+
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "X86RegisterInfo.td"
 include "X86RegisterBanks.td"
 
 //===----------------------------------------------------------------------===//

 ]>;
 def : GoldmontPlusProc<"goldmont-plus">;
 
 class TremontProc<string Name> : ProcModel<Name, SLMModel,
       GLMFeatures.Value, [
   ProcIntelTRM,
   FeatureCLDEMOTE,
   FeatureGFNI,
+  FeatureMOVDIRI,
+  FeatureMOVDIR64B,
   FeatureRDPID,
   FeatureSGX,
   FeatureWAITPKG
 ]>;
 def : TremontProc<"tremont">;
 
 // "Arrandale" along with corei3 and corei5
 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [

lib/Target/X86/X86InstrInfo.td

 def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">;
 def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">;
 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
 def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">;
 def HasLAHFSAHF  : Predicate<"Subtarget->hasLAHFSAHF()">;
 def HasMWAITX    : Predicate<"Subtarget->hasMWAITX()">;
 def HasCLZERO    : Predicate<"Subtarget->hasCLZERO()">;
 def HasCLDEMOTE  : Predicate<"Subtarget->hasCLDEMOTE()">;
+def HasMOVDIRI   : Predicate<"Subtarget->hasMOVDIRI()">;
+def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">;
 def FPStackf32   : Predicate<"!Subtarget->hasSSE1()">;
 def FPStackf64   : Predicate<"!Subtarget->hasSSE2()">;
 def HasMPX       : Predicate<"Subtarget->hasMPX()">;
 def HasSHSTK     : Predicate<"Subtarget->hasSHSTK()">;
 def HasIBT       : Predicate<"Subtarget->hasIBT()">;
 def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
 def HasCLWB      : Predicate<"Subtarget->hasCLWB()">;
 def HasWBNOINVD  : Predicate<"Subtarget->hasWBNOINVD()">;

 //===----------------------------------------------------------------------===//
 // Pattern fragments to auto generate TBM instructions.
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasTBM] in {
   // FIXME: patterns for the load versions are not implemented
   def : Pat<(and GR32:$src, (add GR32:$src, 1)),
             (BLCFILL32rr GR32:$src)>;
   def : Pat<(and GR64:$src, (add GR64:$src, 1)),
             (BLCFILL64rr GR64:$src)>;
 
   def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
             (BLCI32rr GR32:$src)>;
   def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
             (BLCI64rr GR64:$src)>;
 
   // Extra patterns because opt can optimize the above patterns to this.

 include "X86InstrSVM.td"
 
 include "X86InstrTSX.td"
 include "X86InstrSGX.td"
 
 // System instructions.
 include "X86InstrSystem.td"
 
+// Direct Move instructions.
+include "X86InstrMovdir.td"
+
 // Compiler Pseudo Instructions and Pat Patterns
 include "X86InstrCompiler.td"
 include "X86InstrVecCompiler.td"
 
 //===----------------------------------------------------------------------===//
 // Assembler Mnemonic Aliases
 //===----------------------------------------------------------------------===//
 

lib/Target/X86/X86InstrMovdir.td

+//===-- X86InstrMovdir.td - Direct Move Instructions ------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+// MOVDIRI - Move doubleword/quadword as direct store
+def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
+                  "movdiri\t{$src, $dst|$dst, $src}",
+                  [(int_x86_directstore32 addr:$dst, GR32:$src)]>,
+                 T8, Requires<[HasMOVDIRI]>;
+def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
+                   "movdiri\t{$src, $dst|$dst, $src}",
+                   [(int_x86_directstore64 addr:$dst, GR64:$src)]>,
+                  T8, Requires<[In64BitMode, HasMOVDIRI]>;
+
+// MOVDIR64B - Move 64 bytes as direct store
+def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src),
+                    "movdir64b\t{$src, $dst|$dst, $src}", []>,
+                   T8PD, AdSize16, Requires<[HasMOVDIR64B, Not64BitMode]>;
+def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src),
+                    "movdir64b\t{$src, $dst|$dst, $src}",
+                    [(int_x86_movdir64b GR32:$dst, addr:$src)]>,
+                   T8PD, AdSize32, Requires<[HasMOVDIR64B]>;
+def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src),
+                    "movdir64b\t{$src, $dst|$dst, $src}",
+                    [(int_x86_movdir64b GR64:$dst, addr:$src)]>,
+                   T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>;

lib/Target/X86/X86Subtarget.h

protected:
   bool HasMWAITX;
 
   /// Processor has Cache Line Zero instruction
   bool HasCLZERO;
 
   /// Processor has Cache Line Demote instruction
   bool HasCLDEMOTE;
 
+  /// Processor has MOVDIRI instruction (direct store integer).
+  bool HasMOVDIRI;
+
+  /// Processor has MOVDIR64B instruction (direct store 64 bytes).
+  bool HasMOVDIR64B;
+
   /// Processor has Prefetch with intent to Write instruction
   bool HasPREFETCHWT1;
 
   /// True if SHLD instructions are slow.
   bool IsSHLDSlow;
 
   /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
   //  PMULUDQ.
bool hasSSEPrefetch() const {
     // 3dnow.
     return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
   }
   bool hasRDSEED() const { return HasRDSEED; }
   bool hasLAHFSAHF() const { return HasLAHFSAHF; }
   bool hasMWAITX() const { return HasMWAITX; }
   bool hasCLZERO() const { return HasCLZERO; }
   bool hasCLDEMOTE() const { return HasCLDEMOTE; }
+  bool hasMOVDIRI() const { return HasMOVDIRI; }
+  bool hasMOVDIR64B() const { return HasMOVDIR64B; }
   bool isSHLDSlow() const { return IsSHLDSlow; }
   bool isPMULLDSlow() const { return IsPMULLDSlow; }
   bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
   bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
   int getGatherOverhead() const { return GatherOverhead; }
   int getScatterOverhead() const { return ScatterOverhead; }
   bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
   bool hasCmpxchg16b() const { return HasCmpxchg16b; }

lib/Target/X86/X86Subtarget.cpp

void X86Subtarget::initializeEnvironment() {
   HasSHA = false;
   HasPREFETCHWT1 = false;
   HasPRFCHW = false;
   HasRDSEED = false;
   HasLAHFSAHF = false;
   HasMWAITX = false;
   HasCLZERO = false;
   HasCLDEMOTE = false;
+  HasMOVDIRI = false;
+  HasMOVDIR64B = false;
   HasMPX = false;
   HasSHSTK = false;
   HasIBT = false;
   HasSGX = false;
   HasCLFLUSHOPT = false;
   HasCLWB = false;
   HasWBNOINVD = false;
   HasRDPID = false;

test/CodeGen/X86/movdir-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+movdiri -mattr=+movdir64b | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+movdiri -mattr=+movdir64b | FileCheck %s --check-prefix=X32
+
+define void @test_movdiri(i8* %p, i32 %v) {
+; X64-LABEL: test_movdiri:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    movdiri %esi, (%rdi)
+; X64-NEXT:    retq
+;
+; X32-LABEL: test_movdiri:
+; X32:       # %bb.0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movdiri %eax, (%ecx)
+; X32-NEXT:    retl
+entry:
+  call void @llvm.x86.directstore32(i8* %p, i32 %v)
+  ret void
+}
+
+declare void @llvm.x86.directstore32(i8*, i32)
+
+define void @test_movdir64b(i8* %dst, i8* %src) {
+; X64-LABEL: test_movdir64b:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    movdir64b (%rsi), %rdi
+; X64-NEXT:    retq
+;
+; X32-LABEL: test_movdir64b:
+; X32:       # %bb.0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movdir64b (%eax), %ecx
+; X32-NEXT:    retl
+entry:
+  call void @llvm.x86.movdir64b(i8* %dst, i8* %src)
+  ret void
+}
+
+declare void @llvm.x86.movdir64b(i8*, i8*)

test/CodeGen/X86/movdirq-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+movdiri | FileCheck %s
+
+define void @test_movdiri(i8* %p, i64 %v) {
+; CHECK-LABEL: test_movdiri:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movdiri %rsi, (%rdi)
+; CHECK-NEXT:    retq
+entry:
+  call void @llvm.x86.directstore64(i8* %p, i64 %v)
+  ret void
+}
+
+declare void @llvm.x86.directstore64(i8*, i64)

test/MC/Disassembler/X86/x86-16.txt

 # CHECK: wbnoinvd
 0xf3 0x0f 0x09
 
 # CHECK: umonitor %ax
 0xf3 0x0f 0xae 0xf0
 
 # CHECK: umonitor %eax
 0x67 0xf3 0x0f 0xae 0xf0
+
+#CHECK: movdir64b (%esi), %eax
+0x67 0x66 0x0f 0x38 0xf8 0x06
+
+#CHECK: movdir64b (%si), %ax
+0x66 0x0f 0x38 0xf8 0x04

test/MC/Disassembler/X86/x86-32.txt

 # CHECK: umonitor %ax
 0x67 0xf3 0x0f 0xae 0xf0
 
 # CHECK: umwait %eax
 0xf2 0x0f 0xae 0xf0
 
 # CHECK: tpause %eax
 0x66 0x0f 0xae 0xf0
+
+#CHECK: movdiri %eax, 64(%edx,%edi)
+0x0f 0x38 0xf9 0x44 0x3a 0x40
+
+#CHECK: movdir64b 485498096, %ecx
+0x66 0x0f 0x38 0xf8 0x0d 0xf0 0x1c 0xf0 0x1c
+
+#CHECK: movdir64b (%esi), %eax
+0x66 0x0f 0x38 0xf8 0x06
+
+#CHECK: movdir64b (%si), %ax
+0x67 0x66 0x0f 0x38 0xf8 0x04

test/MC/Disassembler/X86/x86-64.txt

 # CHECK: bswapl %bx
 0x66 0x0f 0xcb
 
 # CHECK: bswapl %ebx
 0x0f 0xcb
 
 # CHECK: bswapq %rbx
 0x48 0x0f 0xcb
+
+#CHECK: movdiri %r13d, 64(%rdx,%rax,4)
+0x44 0x0f 0x38 0xf9 0x6c 0x82 0x40
+
+#CHECK: movdir64b 485498096, %rax
+0x66 0x0f 0x38 0xf8 0x04 0x25 0xf0 0x1c 0xf0 0x1c
+
+#CHECK: movdir64b 485498096, %eax
+0x67 0x66 0x0f 0x38 0xf8 0x04 0x25 0xf0 0x1c 0xf0 0x1c

test/MC/X86/x86-16.s

 
 // CHECK: umonitor %ax
 // CHECK:  encoding: [0xf3,0x0f,0xae,0xf0]
 umonitor %ax
 
 // CHECK: umonitor %eax
 // CHECK:  encoding: [0x67,0xf3,0x0f,0xae,0xf0]
 umonitor %eax
+
+// CHECK: movdir64b (%esi), %eax
+// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xf8,0x06]
+movdir64b (%esi), %eax
+
+// CHECK: movdir64b (%si), %ax
+// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x04]
+movdir64b (%si), %ax

test/MC/X86/x86-32-coverage.s

 
 // CHECK: umwait %eax
 // CHECK:  encoding: [0xf2,0x0f,0xae,0xf0]
   umwait %eax
 
 // CHECK: tpause %eax
 // CHECK:  encoding: [0x66,0x0f,0xae,0xf0]
   tpause %eax
+
+// CHECK: movdiri %eax, 64(%edx,%edi)
+// CHECK: # encoding: [0x0f,0x38,0xf9,0x44,0x3a,0x40]
+          movdiri %eax, 64(%edx,%edi)
+
+// CHECK: movdir64b 485498096, %ecx
+// CHECK: # encoding: [0x66,0x0f,0x38,0xf8,0x0d,0xf0,0x1c,0xf0,0x1c]
+          movdir64b 485498096, %ecx
+
+// CHECK: movdir64b 485498096, %cx
+// CHECK: # encoding: [0x67,0x66,0x0f,0x38,0xf8,0x0d,0xf0,0x1c,0xf0,0x1c]
+          movdir64b 485498096, %cx
+
+// CHECK: movdir64b (%edx), %eax
+// CHECK: # encoding: [0x66,0x0f,0x38,0xf8,0x02]
+          movdir64b (%edx), %eax
+
+// CHECK: movdir64b (%esi), %eax
+// CHECK: # encoding: [0x66,0x0f,0x38,0xf8,0x06]
+          movdir64b (%esi), %eax
+
+// CHECK: movdir64b (%si), %ax
+// CHECK: # encoding: [0x67,0x66,0x0f,0x38,0xf8,0x04]
+          movdir64b (%si), %ax

test/MC/X86/x86-64.s

 // CHECK: tpause %r15
 // CHECK:  encoding: [0x66,0x41,0x0f,0xae,0xf7]
 tpause %r15
 
 // CHECK: tpause %ebx
 // CHECK:  encoding: [0x66,0x0f,0xae,0xf3]
 tpause %ebx
 
+// CHECK: movdiri %r15, 485498096
+// CHECK: # encoding: [0x4c,0x0f,0x38,0xf9,0x3c,0x25,0xf0,0x1c,0xf0,0x1c]
+movdiri %r15, 485498096
+
+// CHECK: movdiri %r15, (%rdx)
+// CHECK: # encoding: [0x4c,0x0f,0x38,0xf9,0x3a]
+movdiri %r15, (%rdx)
+
+// CHECK: movdiri %r15, 64(%rdx)
+// CHECK: # encoding: [0x4c,0x0f,0x38,0xf9,0x7a,0x40]
+movdiri %r15, 64(%rdx)
+
+// CHECK: movdir64b 485498096, %rax
+// CHECK: # encoding: [0x66,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
+movdir64b 485498096, %rax
+
+// CHECK: movdir64b 485498096, %eax
+// CHECK: # encoding: [0x67,0x66,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
+movdir64b 485498096, %eax
+
+// CHECK: movdir64b (%rdx), %r15
+// CHECK: # encoding: [0x66,0x44,0x0f,0x38,0xf8,0x3a]
+movdir64b (%rdx), %r15
+
 //  __asm __volatile(
 //    "pushf        \n\t"
 //    "popf       \n\t"
 //    "rep        \n\t"
 //    ".byte  0x0f, 0xa7, 0xd0"
 //  );
 // CHECK: pushfq
 // CHECK-NEXT: popfq

utils/TableGen/X86RecognizableInstr.cpp

if (Encoding == X86Local::EVEX) {
     if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
       insnContext = IC_64BIT_REXW_OPSIZE;
     else if (HasREX_WPrefix && AdSize == X86Local::AdSize32)
       insnContext = IC_64BIT_REXW_ADSIZE;
     else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
       insnContext = IC_64BIT_XD_OPSIZE;
     else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
       insnContext = IC_64BIT_XS_OPSIZE;
+    else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD)
+      insnContext = IC_64BIT_OPSIZE_ADSIZE;
     else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
       insnContext = IC_64BIT_OPSIZE_ADSIZE;
     else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
       insnContext = IC_64BIT_OPSIZE;
     else if (AdSize == X86Local::AdSize32)
       insnContext = IC_64BIT_ADSIZE;
     else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
       insnContext = IC_64BIT_REXW_XS;
if (Encoding == X86Local::EVEX) {
     if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
       insnContext = IC_XD_OPSIZE;
     else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
       insnContext = IC_XS_OPSIZE;
     else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD)
       insnContext = IC_XD_ADSIZE;
     else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS)
       insnContext = IC_XS_ADSIZE;
+    else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD)
+      insnContext = IC_OPSIZE_ADSIZE;
     else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
       insnContext = IC_OPSIZE_ADSIZE;
     else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
       insnContext = IC_OPSIZE;
     else if (AdSize == X86Local::AdSize16)
       insnContext = IC_ADSIZE;
     else if (OpPrefix == X86Local::XD)
       insnContext = IC_XD;