[mips] Fix the definition of sync, synci

[sdardis]

Summary

Also, fix the disassembly of synci for microMIPS.

[sdardis]

Fix definition of 'sync 0' alias for microMIPS.

[atanasyan]

LGTM

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
                                     uint64_t Address,
                                     const void *Decoder);
 
 static DecodeStatus DecodeSyncI(MCInst &Inst,
                                 unsigned Insn,
                                 uint64_t Address,
                                 const void *Decoder);
 
+static DecodeStatus DecodeSyncI_MM(MCInst &Inst,
+                                   unsigned Insn,
+                                   uint64_t Address,
+                                   const void *Decoder);
+
 static DecodeStatus DecodeSynciR6(MCInst &Inst,
                                   unsigned Insn,
                                   uint64_t Address,
                                   const void *Decoder);
 
 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
                                     uint64_t Address, const void *Decoder);
 
static DecodeStatus DecodeSyncI(MCInst &Inst,
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
 
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
+                                   uint64_t Address, const void *Decoder) {
+  int Offset = SignExtend32<16>(Insn & 0xffff);
+  unsigned Base = fieldFromInstruction(Insn, 16, 5);
+
+  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
+
+  Inst.addOperand(MCOperand::createReg(Base));
+  Inst.addOperand(MCOperand::createImm(Offset));
+
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeSynciR6(MCInst &Inst,
                                   unsigned Insn,
                                   uint64_t Address,
                                   const void *Decoder) {
   int Immediate = SignExtend32<16>(Insn & 0xffff);
   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);

lib/Target/Mips/MicroMips32r6InstrInfo.td

class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
   dag OutOperandList = (outs);
   dag InOperandList = (ins uimm5:$stype);
   string AsmString = !strconcat("sync", "\t$stype");
   list<dag> Pattern = [(MipsSync immZExt5:$stype)];
   InstrItinClass Itinerary = II_SYNC;
   bit HasSideEffects = 1;
 }
 
-class SYNCI_MMR6_DESC : SYNCI_FT<"synci"> {
+class SYNCI_MMR6_DESC : SYNCI_FT<"synci", mem_mm_16> {
   let DecoderMethod = "DecodeSynciR6";
 }
 
 class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
   dag OutOperandList = (outs GPR32Opnd:$rt);
   dag InOperandList = (ins GPR32Opnd:$rd);
   string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
   InstrItinClass Itinerary = II_RDPGPR;

lib/Target/Mips/MicroMipsInstrFormats.td

class SYNC_FM_MM : MMArch {
   let Inst{31-26} = 0x00;
   let Inst{25-21} = 0x0;
   let Inst{20-16} = stype;
   let Inst{15-6}  = 0x1ad;
   let Inst{5-0}   = 0x3c;
 }
 
 class SYNCI_FM_MM : MMArch {
-  bits<5> rs;
-  bits<16> offset;
+  bits<21> addr;
+  bits<5> rs = addr{20-16};
+  bits<16> offset = addr{15-0};
   bits<32> Inst;
 
   let Inst{31-26} = 0b010000;
   let Inst{25-21} = 0b10000;
   let Inst{20-16} = rs;
   let Inst{15-0}  = offset;
 }
 

lib/Target/Mips/MicroMipsInstrInfo.td

def mem_mm_12 : Operand<i32> {
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
 }
 
 def mem_mm_16 : Operand<i32> {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops ptr_rc, simm16);
   let EncoderMethod = "getMemEncodingMMImm16";
+  let DecoderMethod = "DecodeMemMMImm16";
   let ParserMatchClass = MipsMemSimm16AsmOperand;
   let OperandType = "OPERAND_MEMORY";
 }
 
 def MipsMemUimm4AsmOperand : AsmOperandClass {
   let Name = "MemOffsetUimm4";
   let SuperClasses = [MipsMemAsmOperand];
   let RenderMethod = "addMemOperands";
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
 
   /// Branch Instructions - Short Delay Slot
   def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
                                              GPR32Opnd>, BGEZAL_FM_MM<0x13>;
   def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
                                              GPR32Opnd>, BGEZAL_FM_MM<0x11>;
 }
 def B_MM    : UncondBranch<BEQ_MM, brtarget_mm>, IsBranch, ISA_MICROMIPS;
-let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
+let DecoderNamespace = "MicroMips" in {
 
   /// Control Instructions
-  def SYNC_MM    : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
-  def SYNCI_MM   : MMRel, SYNCI_FT<"synci">, SYNCI_FM_MM;
+  def SYNC_MM    : MMRel, SYNC_FT<"sync">, SYNC_FM_MM, ISA_MICROMIPS;
+  let DecoderMethod = "DecodeSyncI_MM" in
+    def SYNCI_MM   : MMRel, SYNCI_FT<"synci", mem_mm_16>, SYNCI_FM_MM,
+                     ISA_MICROMIPS32_NOT_MIPS32R6;
+  let Predicates = [InMicroMips] in {
   def BREAK_MM   : MMRel, BRK_FT<"break">, BRK_FM_MM;
   def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM;
   def WAIT_MM    : WaitMM<"wait">, WAIT_FM_MM;
   def ERET_MM    : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>;
   def DERET_MM   : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>;
   def EI_MM      : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>,
                    ISA_MIPS32R2;
   def DI_MM      : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>,
let DecoderNamespace = "MicroMips" in {
   def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>,
                  TEQI_FM_MM<0x0a>;
   def TNEI_MM  : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM_MM<0x0c>;
 
   /// Load-linked, Store-conditional
   def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
   def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
 }
+}
 let DecoderNamespace = "MicroMips" in {
   def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>,
                ISA_MICROMIPS, ASE_EVA;
   def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>,
                ISA_MICROMIPS, ASE_EVA;
 }
 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
   let DecoderMethod = "DecodeCacheOpMM" in {
let Predicates = [InMicroMips] in {
   def : MipsInstAlias<"sra $rd, $shamt",
                       (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
   def : MipsInstAlias<"srl $rd, $shamt",
                       (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
   def : MipsInstAlias<"rotr $rt, $imm",
                       (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
   def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
 
+  def : MipsInstAlias<"sync", (SYNC_MM 0), 1>, ISA_MICROMIPS32_NOT_MIPS32R6;
+
   defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>, ISA_MICROMIPS;
 
   defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>, ISA_MICROMIPS;
 
   defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi_MM>, ISA_MICROMIPS;
 
   defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi_MM>, ISA_MICROMIPS;
 

lib/Target/Mips/MipsInstrInfo.td

InstSE<(outs RO:$rt), (ins),
          !strconcat(opstr, "\t$rt"), [], itin, FrmOther, opstr>;
 
 // Sync
 let hasSideEffects = 1 in
 class SYNC_FT<string opstr> :
   InstSE<(outs), (ins uimm5:$stype), "sync $stype",
          [(MipsSync immZExt5:$stype)], II_SYNC, FrmOther, opstr>;
 
-class SYNCI_FT<string opstr> :
-  InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
+class SYNCI_FT<string opstr, DAGOperand MO> :
+  InstSE<(outs), (ins MO:$addr), !strconcat(opstr, "\t$addr"), [],
          II_SYNCI, FrmOther, opstr> {
   let hasSideEffects = 1;
   let DecoderMethod = "DecodeSyncI";
 }
 
 let hasSideEffects = 1, isCTI = 1 in {
 class TEQ_FT<string opstr, RegisterOperand RO, Operand ImmOp,
              InstrItinClass itin = NoItinerary> :
def SWC3 : SW_FT3<"swc3", COP3Opnd, II_SWC3, store>, LW_FM<0x3b>,
              ISA_MIPS1_NOT_32R6_64R6, NOT_ASE_CNMIPS;
   def LDC3 : LW_FT3<"ldc3", COP3Opnd, II_LDC3, load>, LW_FM<0x37>,
              ISA_MIPS2, NOT_ASE_CNMIPS;
   def SDC3 : SW_FT3<"sdc3", COP3Opnd, II_SDC3, store>, LW_FM<0x3f>,
              ISA_MIPS2, NOT_ASE_CNMIPS;
 }
 
   def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2;
-  def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
+  def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci", mem_simm16>, SYNCI_FM,
+              ISA_MIPS32R2;
 }
 
 let AdditionalPredicates = [NotInMicroMips] in {
   def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>, ISA_MIPS2;
   def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10, II_TGE>, TEQ_FM<0x30>, ISA_MIPS2;
   def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10, II_TGEU>, TEQ_FM<0x31>, ISA_MIPS2;
   def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm10, II_TLT>, TEQ_FM<0x32>, ISA_MIPS2;
   def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10, II_TLTU>, TEQ_FM<0x33>, ISA_MIPS2;
let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsInstAlias<"srl $rd, $rt",
                       (SRLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
   def : MipsInstAlias<"seh $rd", (SEH GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
                      ISA_MIPS32R2;
   def : MipsInstAlias<"seb $rd", (SEB GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
                      ISA_MIPS32R2;
 }
 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
-def : MipsInstAlias<"sync",
-                    (SYNC 0), 1>, ISA_MIPS2;
+let AdditionalPredicates = [NotInMicroMips] in
+  def : MipsInstAlias<"sync", (SYNC 0), 1>, ISA_MIPS2;
 
 def : MipsInstAlias<"mulo $rs, $rt",
                     (MULOMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
                     ISA_MIPS1_NOT_32R6_64R6;
 def : MipsInstAlias<"mulou $rs, $rt",
                     (MULOUMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
                     ISA_MIPS1_NOT_32R6_64R6;
 

test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

 0x82 0x54 0xb0 0x01 # CHECK: mul.d $f0, $f2, $f4
 0x82 0x54 0xf0 0x01 # CHECK: div.d $f0, $f2, $f4
 0x02 0x54 0x7b 0x20 # CHECK: mov.d $f0, $f2
 0x02 0x54 0x7b 0x2b # CHECK: neg.d $f0, $f2
 0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2
 0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2
 0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2
 0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2
+0x07 0x00 0x7c 0x6b # CHECK: sync  7
+0x03 0x42 0x00 0x04 # CHECK: synci 1024($3)

test/MC/Mips/micromips/valid.s

 bc1t 8                      # CHECK: bc1t 8                     # encoding: [0x43,0xa0,0x00,0x04]
                             # CHECK-NEXT:                       # <MCInst #{{[0-9]+}} BC1T_MM
 bc1f 16                     # CHECK: bc1f 16                    # encoding: [0x43,0x80,0x00,0x08]
                             # CHECK-NEXT:                       # <MCInst #{{[0-9]+}} BC1F_MM
 bc1t $fcc1, 4               # CHECK: bc1t $fcc1, 4              # encoding: [0x43,0xa4,0x00,0x02]
                             # CHECK-NEXT:                       # <MCInst #{{[0-9]+}} BC1T_MM
 bc1f $fcc2, -20             # CHECK: bc1f $fcc2, -20            # encoding: [0x43,0x88,0xff,0xf6]
                             # CHECK-NEXT:                       # <MCInst #{{[0-9]+}} BC1F_MM
-sync                        # CHECK: sync                   # encoding: [0x00,0x00,0x6b,0x7c]
-sync 0                      # CHECK: sync 0                 # encoding: [0x00,0x00,0x6b,0x7c]
-sync 1                      # CHECK: sync 1                 # encoding: [0x00,0x01,0x6b,0x7c]
-synci 64($5)                # CHECK: synci 64($5)           # encoding: [0x42,0x00,0x00,0x40]
+sync                        # CHECK: sync                       # encoding: [0x00,0x00,0x6b,0x7c]
+                            # CHECK-NEXT:                       # <MCInst #{{[0-9]+}} SYNC_MM
+sync 0                      # CHECK: sync                       # encoding: [0x00,0x00,0x6b,0x7c]
+                            # CHECK-NEXT:                       # <MCInst #{{[0-9]+}} SYNC_MM
+sync 1                      # CHECK: sync 1                     # encoding: [0x00,0x01,0x6b,0x7c]
+                            # CHECK-NEXT:                       # <MCInst #{{[0-9]+}} SYNC_MM
+synci 64($5)                # CHECK: synci 64($5)               # encoding: [0x42,0x05,0x00,0x40]
+                            # CHECK-NEXT:                       # <MCInst #{{[0-9]+}} SYNCI_MM
+

test/MC/Mips/mips32r2/valid.s

a:
         suxc1     $f12,$k1($13)
         sw        $ra,-10160($sp)
         swc1      $f6,-8465($24)
         swc2      $25,24880($s0)       # CHECK: swc2 $25, 24880($16)   # encoding: [0xea,0x19,0x61,0x30]
         swl       $15,13694($s3)
         swr       $s1,-26590($14)
         swxc1     $f19,$12($k0)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+                                       #!CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+                                       #!CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         syscall                        # CHECK: syscall                # encoding: [0x00,0x00,0x00,0x0c]
         syscall   256                  # CHECK: syscall 256            # encoding: [0x00,0x00,0x40,0x0c]
         teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
                                        # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TEQ
                                        # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TEQ_MM
         teq       $5,$7,620            # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
                                        # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TEQ
                                        # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TEQ_MM
a:
                                        # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TNEI_MM
         trunc.w.d $f22,$f15            # CHECK: trunc.w.d $f22, $f14   # encoding: [0x46,0x20,0x75,0x8d]
         trunc.w.s $f28,$f30            # CHECK: trunc.w.s $f28, $f30   # encoding: [0x46,0x00,0xf7,0x0d]
         trunc.w.d $f4,$f6,$4           # CHECK: trunc.w.d $f4, $f6     # encoding: [0x46,0x20,0x31,0x0d]
         trunc.w.s $f4,$f6,$4           # CHECK: trunc.w.s $f4, $f6     # encoding: [0x46,0x00,0x31,0x0d]
         wsbh      $k1,$9
         xor       $s2,$a0,$s8
         xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
-        synci     -15842($a2)          # CHECK: synci -15842($6)        # encoding: [0x04,0xdf,0xc2,0x1e]
+        synci     -15842($a2)          # CHECK: synci -15842($6)       # encoding: [0x04,0xdf,0xc2,0x1e]
+                                       #!CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNCI
 
 1:
 
         # Check that we accept traditional %relocation(symbol) offsets for stores
         # and loads, not just a sign 16 bit offset.
 
         lui       $2, %hi(g_8)            # CHECK:  encoding: [0x3c,0x02,A,A]
         lb        $3, %lo(g_8)($2)        # CHECK:  encoding: [0x80,0x43,A,A]

test/MC/Mips/mips32r3/valid.s

a:
         suxc1     $f12,$k1($13)
         sw        $ra,-10160($sp)
         swc1      $f6,-8465($24)
         swc2      $25,24880($s0)       # CHECK: swc2 $25, 24880($16)   # encoding: [0xea,0x19,0x61,0x30]
         swl       $15,13694($s3)
         swr       $s1,-26590($14)
         swxc1     $f19,$12($k0)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         syscall                        # CHECK: syscall                # encoding: [0x00,0x00,0x00,0x0c]
         syscall   256                  # CHECK: syscall 256            # encoding: [0x00,0x00,0x40,0x0c]
         teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
                                        # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TEQ
                                        # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TEQ_MM
         teq       $5,$7,620            # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
                                        # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TEQ
                                        # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TEQ_MM
a:
                                        # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TNEI_MM
         trunc.w.d $f22,$f15            # CHECK: trunc.w.d $f22, $f14   # encoding: [0x46,0x20,0x75,0x8d]
         trunc.w.s $f28,$f30            # CHECK: trunc.w.s $f28, $f30   # encoding: [0x46,0x00,0xf7,0x0d]
         trunc.w.d $f4,$f6,$4           # CHECK: trunc.w.d $f4, $f6     # encoding: [0x46,0x20,0x31,0x0d]
         trunc.w.s $f4,$f6,$4           # CHECK: trunc.w.s $f4, $f6     # encoding: [0x46,0x00,0x31,0x0d]
         wsbh      $k1,$9
         xor       $s2,$a0,$s8
         xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
-        synci     -15842($a2)          # CHECK: synci -15842($6)        # encoding: [0x04,0xdf,0xc2,0x1e]
+        synci     -15842($a2)          # CHECK: synci -15842($6)       # encoding: [0x04,0xdf,0xc2,0x1e]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNCI
 
 1:
 
         # Check that we accept traditional %relocation(symbol) offsets for stores
         # and loads, not just a sign 16 bit offset.
 
         lui       $2, %hi(g_8)            # CHECK:  encoding: [0x3c,0x02,A,A]
         lb        $3, %lo(g_8)($2)        # CHECK:  encoding: [0x80,0x43,A,A]

test/MC/Mips/mips32r5/valid.s

a:
         suxc1     $f12,$k1($13)
         sw        $ra,-10160($sp)
         swc1      $f6,-8465($24)
         swc2      $25,24880($s0)       # CHECK: swc2 $25, 24880($16)   # encoding: [0xea,0x19,0x61,0x30]
         swl       $15,13694($s3)
         swr       $s1,-26590($14)
         swxc1     $f19,$12($k0)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         syscall                        # CHECK: syscall                # encoding: [0x00,0x00,0x00,0x0c]
         syscall   256                  # CHECK: syscall 256            # encoding: [0x00,0x00,0x40,0x0c]
         teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
                                        # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TEQ
                                        # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TEQ_MM
         teq       $5,$7,620            # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
                                        # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TEQ
                                        # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TEQ_MM
a:
         trunc.w.d $f22,$f15            # CHECK: trunc.w.d $f22, $f14   # encoding: [0x46,0x20,0x75,0x8d]
         trunc.w.s $f28,$f30            # CHECK: trunc.w.s $f28, $f30   # encoding: [0x46,0x00,0xf7,0x0d]
         trunc.w.d $f4,$f6,$4           # CHECK: trunc.w.d $f4, $f6     # encoding: [0x46,0x20,0x31,0x0d]
         trunc.w.s $f4,$f6,$4           # CHECK: trunc.w.s $f4, $f6     # encoding: [0x46,0x00,0x31,0x0d]
         wsbh      $k1,$9
         xor       $s2,$a0,$s8
         xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
         synci     -15842($a2)          # CHECK: synci -15842($6)        # encoding: [0x04,0xdf,0xc2,0x1e]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNCI
 
 1:
 
         # Check that we accept traditional %relocation(symbol) offsets for stores
         # and loads, not just a sign 16 bit offset.
 
         lui       $2, %hi(g_8)            # CHECK:  encoding: [0x3c,0x02,A,A]
         lb        $3, %lo(g_8)($2)        # CHECK:  encoding: [0x80,0x43,A,A]

test/MC/Mips/mips32r6/valid.s

a:
         ssnop                    # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
         sdbbp                    # CHECK: sdbbp                  # encoding: [0x00,0x00,0x00,0x0e]
                                  # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SDBBP
                                  # CHECK-NOT:                    # <MCInst #{{[0-9]+}} SDBBP_MM
         sdbbp     34             # CHECK: sdbbp 34               # encoding: [0x00,0x00,0x08,0x8e]
                                  # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SDBBP
                                  # CHECK-NOT:                    # <MCInst #{{[0-9]+}} SDBBP_MM
         sync                     # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+                                 # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         sync    1                # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+                                 # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         syscall                  # CHECK: syscall                # encoding: [0x00,0x00,0x00,0x0c]
         syscall   256            # CHECK: syscall 256            # encoding: [0x00,0x00,0x40,0x0c]
         tlbp                     # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
                                  # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TLBP
                                  # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TLBP_MM
         tlbr                     # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
                                  # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TLBR
                                  # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TLBR_MM
a:
                                  # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TLTU_MM
         tne     $6,$17           # CHECK: tne $6, $17            # encoding: [0x00,0xd1,0x00,0x36]
                                  # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TNE
                                  # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TNE_MM
         tne     $7,$8,885        # CHECK: tne $7, $8, 885        # encoding: [0x00,0xe8,0xdd,0x76]
                                  # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TNE
                                  # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TNE_MM
         xor     $2, 4            # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
+        synci     -15842($a2)    # CHECK: synci -15842($6)       # encoding: [0x04,0xdf,0xc2,0x1e]
+                                 # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNCI
 
 1:
 
         # Check that we accept traditional %relocation(symbol) offsets for stores
         # and loads, not just a sign 16 bit offset.
 
         lui     $2, %hi(g_8)            # CHECK:  encoding: [0x3c,0x02,A,A]
         lb      $3, %lo(g_8)($2)        # CHECK:  encoding: [0x80,0x43,A,A]

test/MC/Mips/mips64r2/valid.s

a:
         suxc1     $f12,$k1($13)
         sw        $ra,-10160($sp)
         swc1      $f6,-8465($24)
         swc2      $25,24880($s0)       # CHECK: swc2 $25, 24880($16)   # encoding: [0xea,0x19,0x61,0x30]
         swl       $15,13694($s3)
         swr       $s1,-26590($14)
         swxc1     $f19,$12($k0)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         syscall                        # CHECK: syscall                # encoding: [0x00,0x00,0x00,0x0c]
         syscall   256                  # CHECK: syscall 256            # encoding: [0x00,0x00,0x40,0x0c]
         teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
                                        # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TEQ
                                        # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TEQ_MM
         teq       $5,$7,620            # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
                                        # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TEQ
                                        # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TEQ_MM
a:
         trunc.l.s $f28,$f31            # CHECK: trunc.l.s $f28, $f31   # encoding: [0x46,0x00,0xff,0x09]
         trunc.w.d $f22,$f15            # CHECK: trunc.w.d $f22, $f15   # encoding: [0x46,0x20,0x7d,0x8d]
         trunc.w.s $f28,$f30            # CHECK: trunc.w.s $f28, $f30   # encoding: [0x46,0x00,0xf7,0x0d]
         trunc.w.d $f4,$f6,$4           # CHECK: trunc.w.d $f4, $f6     # encoding: [0x46,0x20,0x31,0x0d]
         trunc.w.s $f4,$f6,$4           # CHECK: trunc.w.s $f4, $f6     # encoding: [0x46,0x00,0x31,0x0d]
         xor       $s2,$a0,$s8
         xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
         wsbh      $k1,$9
+        synci     -15842($a2)          # CHECK: synci -15842($6)       # encoding: [0x04,0xdf,0xc2,0x1e]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
 
 1:
 
         # Check that we accept traditional %relocation(symbol) offsets for stores
         # and loads, not just a sign 16 bit offset.
 
         lui       $2, %hi(g_8)            # CHECK:  encoding: [0x3c,0x02,A,A]
         lb        $3, %lo(g_8)($2)        # CHECK:  encoding: [0x80,0x43,A,A]

test/MC/Mips/mips64r3/valid.s

a:
         suxc1     $f12,$k1($13)
         sw        $ra,-10160($sp)
         swc1      $f6,-8465($24)
         swc2      $25,24880($s0)       # CHECK: swc2 $25, 24880($16)   # encoding: [0xea,0x19,0x61,0x30]
         swl       $15,13694($s3)
         swr       $s1,-26590($14)
         swxc1     $f19,$12($k0)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         syscall                        # CHECK: syscall                # encoding: [0x00,0x00,0x00,0x0c]
         syscall   256                  # CHECK: syscall 256            # encoding: [0x00,0x00,0x40,0x0c]
         teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
                                        # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TEQ
                                        # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TEQ_MM
         teq       $5,$7,620            # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
                                        # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TEQ
                                        # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TEQ_MM
a:
         trunc.l.s $f28,$f31            # CHECK: trunc.l.s $f28, $f31   # encoding: [0x46,0x00,0xff,0x09]
         trunc.w.d $f22,$f15            # CHECK: trunc.w.d $f22, $f15   # encoding: [0x46,0x20,0x7d,0x8d]
         trunc.w.s $f28,$f30            # CHECK: trunc.w.s $f28, $f30   # encoding: [0x46,0x00,0xf7,0x0d]
         trunc.w.d $f4,$f6,$4           # CHECK: trunc.w.d $f4, $f6     # encoding: [0x46,0x20,0x31,0x0d]
         trunc.w.s $f4,$f6,$4           # CHECK: trunc.w.s $f4, $f6     # encoding: [0x46,0x00,0x31,0x0d]
         xor       $s2,$a0,$s8
         xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
         wsbh      $k1,$9
+        synci     -15842($a2)          # CHECK: synci -15842($6)       # encoding: [0x04,0xdf,0xc2,0x1e]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNCI
 
 1:
 
         # Check that we accept traditional %relocation(symbol) offsets for stores
         # and loads, not just a sign 16 bit offset.
 
         lui       $2, %hi(g_8)            # CHECK:  encoding: [0x3c,0x02,A,A]
         lb        $3, %lo(g_8)($2)        # CHECK:  encoding: [0x80,0x43,A,A]

test/MC/Mips/mips64r5/valid.s

a:
         suxc1     $f12,$k1($13)
         sw        $ra,-10160($sp)
         swc1      $f6,-8465($24)
         swc2      $25,24880($s0)       # CHECK: swc2 $25, 24880($16)   # encoding: [0xea,0x19,0x61,0x30]
         swl       $15,13694($s3)
         swr       $s1,-26590($14)
         swxc1     $f19,$12($k0)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         syscall                        # CHECK: syscall                # encoding: [0x00,0x00,0x00,0x0c]
         syscall   256                  # CHECK: syscall 256            # encoding: [0x00,0x00,0x40,0x0c]
         teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
                                        # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TEQ
                                        # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TEQ_MM
         teq       $5,$7,620            # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
                                        # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TEQ
                                        # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TEQ_MM
a:
         trunc.l.s $f28,$f31            # CHECK: trunc.l.s $f28, $f31   # encoding: [0x46,0x00,0xff,0x09]
         trunc.w.d $f22,$f15            # CHECK: trunc.w.d $f22, $f15   # encoding: [0x46,0x20,0x7d,0x8d]
         trunc.w.s $f28,$f30            # CHECK: trunc.w.s $f28, $f30   # encoding: [0x46,0x00,0xf7,0x0d]
         trunc.w.d $f4,$f6,$4           # CHECK: trunc.w.d $f4, $f6     # encoding: [0x46,0x20,0x31,0x0d]
         trunc.w.s $f4,$f6,$4           # CHECK: trunc.w.s $f4, $f6     # encoding: [0x46,0x00,0x31,0x0d]
         xor       $s2,$a0,$s8
         xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
         wsbh      $k1,$9
+        synci     -15842($a2)          # CHECK: synci -15842($6)       # encoding: [0x04,0xdf,0xc2,0x1e]
+                                       # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNCI
 
 1:
 
         # Check that we accept traditional %relocation(symbol) offsets for stores
         # and loads, not just a sign 16 bit offset.
 
         lui       $2, %hi(g_8)            # CHECK:  encoding: [0x3c,0x02,A,A]
         lb        $3, %lo(g_8)($2)        # CHECK:  encoding: [0x80,0x43,A,A]

test/MC/Mips/mips64r6/valid.s

a:
         sgtu    $4, $5, $6       # CHECK: sltu $4, $6, $5        # encoding: [0x00,0xc5,0x20,0x2b]
         sll     $4, $5           # CHECK: sllv $4, $4, $5        # encoding: [0x00,0xa4,0x20,0x04]
         sra     $4, $5           # CHECK: srav $4, $4, $5        # encoding: [0x00,0xa4,0x20,0x07]
         srl     $4, $5           # CHECK: srlv $4, $4, $5        # encoding: [0x00,0xa4,0x20,0x06]
         ssnop                    # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
         ssnop                    # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction
         swc2    $25,304($s0)     # CHECK: swc2 $25, 304($16)     # encoding: [0x49,0x79,0x81,0x30]
         sync                     # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+                                 # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         sync    1                # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+                                 # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNC
         syscall                  # CHECK: syscall                # encoding: [0x00,0x00,0x00,0x0c]
         syscall   256            # CHECK: syscall 256            # encoding: [0x00,0x00,0x40,0x0c]
         tlbp                     # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
                                  # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TLBP
                                  # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TLBP_MM
         tlbr                     # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
                                  # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} TLBR
                                  # CHECK-NOT:                    # <MCInst #{{[0-9]+}} TLBR_MM
a:
         tgeu    $22,$28          # CHECK: tgeu $22, $gp          # encoding: [0x02,0xdc,0x00,0x31]
         tlt     $15,$13          # CHECK: tlt $15, $13           # encoding: [0x01,0xed,0x00,0x32]
         tlt     $2,$19,133       # CHECK: tlt $2, $19, 133       # encoding: [0x00,0x53,0x21,0x72]
         tltu    $11,$16          # CHECK: tltu $11, $16          # encoding: [0x01,0x70,0x00,0x33]
         tltu    $16,$29,1016     # CHECK: tltu $16, $sp, 1016    # encoding: [0x02,0x1d,0xfe,0x33]
         tne     $6,$17           # CHECK: tne $6, $17            # encoding: [0x00,0xd1,0x00,0x36]
         tne     $7,$8,885        # CHECK: tne $7, $8, 885        # encoding: [0x00,0xe8,0xdd,0x76]
         xor     $2, 4            # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
-
+        synci     -15842($a2)    # CHECK: synci -15842($6)       # encoding: [0x04,0xdf,0xc2,0x1e]
+                                 # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} SYNCI
 1:
 
         # Check that we accept traditional %relocation(symbol) offsets for stores
         # and loads, not just a sign 16 bit offset.
 
         lui     $2, %hi(g_8)            # CHECK:  encoding: [0x3c,0x02,A,A]
         lb      $3, %lo(g_8)($2)        # CHECK:  encoding: [0x80,0x43,A,A]
         lh      $3, %lo(g_8)($2)        # CHECK:  encoding: [0x84,0x43,A,A]