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Differential D45870

[mips] Fix the definition of sync, synci
ClosedPublic

Authored by sdardis on Apr 20 2018, 3:52 AM.

Details

Reviewers
abeserminji
smaksimovic
atanasyan
Commits
rGeac9301cdbf5: [mips] Fix the definition of sync, synci
rL330810: [mips] Fix the definition of sync, synci
Summary

Also, fix the disassembly of synci for microMIPS.

Diff Detail

Repository
rL LLVM

Event Timeline

sdardis created this revision.Apr 20 2018, 3:52 AM
Herald added a subscriber: arichardson. · View Herald TranscriptApr 20 2018, 3:52 AM
sdardis updated this revision to Diff 143516.Apr 23 2018, 2:47 AM

Fix definition of 'sync 0' alias for microMIPS.

atanasyan accepted this revision.Apr 24 2018, 8:57 AM

LGTM

This revision is now accepted and ready to land.Apr 24 2018, 8:57 AM
Closed by commit rL330810: [mips] Fix the definition of sync, synci (authored by sdardis). · Explain WhyApr 25 2018, 3:23 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
Disassembler/
18 lines
2 lines
5 lines
11 lines
11 lines
test/
MC/
Disassembler/
Mips/
micromips32r3/
2 lines
Mips/
micromips/
13 lines
mips32r2/
5 lines
mips32r3/
5 lines
mips32r5/
3 lines
mips32r6/
4 lines
mips64r2/
4 lines
mips64r3/
4 lines
mips64r5/
4 lines
mips64r6/
5 lines

Diff 143890

llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Show First 20 Lines • Show All 299 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodePrefeOpMM(MCInst &Inst,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeSyncI(MCInst &Inst, static DecodeStatus DecodeSyncI(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeSyncI_MM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeSynciR6(MCInst &Inst, static DecodeStatus DecodeSynciR6(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
▲ Show 20 Lines • Show All 1,328 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeSyncI(MCInst &Inst,
Base = getReg(Decoder, Mips::GPR32RegClassID, Base); Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::createReg(Base)); Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset)); Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0xffff);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeSynciR6(MCInst &Inst, static DecodeStatus DecodeSynciR6(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
int Immediate = SignExtend32<16>(Insn & 0xffff); int Immediate = SignExtend32<16>(Insn & 0xffff);
unsigned Base = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 16, 5);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base); Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
▲ Show 20 Lines • Show All 909 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

Show First 20 Lines • Show All 1,121 Lines • ▼ Show 20 Linesclass SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
dag OutOperandList = (outs); dag OutOperandList = (outs);
dag InOperandList = (ins uimm5:$stype); dag InOperandList = (ins uimm5:$stype);
string AsmString = !strconcat("sync", "\t$stype"); string AsmString = !strconcat("sync", "\t$stype");
list<dag> Pattern = [(MipsSync immZExt5:$stype)]; list<dag> Pattern = [(MipsSync immZExt5:$stype)];
InstrItinClass Itinerary = II_SYNC; InstrItinClass Itinerary = II_SYNC;
bit HasSideEffects = 1; bit HasSideEffects = 1;
} }
class SYNCI_MMR6_DESC : SYNCI_FT<"synci"> { class SYNCI_MMR6_DESC : SYNCI_FT<"synci", mem_mm_16> {
let DecoderMethod = "DecodeSynciR6"; let DecoderMethod = "DecodeSynciR6";
} }
class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst { class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
dag OutOperandList = (outs GPR32Opnd:$rt); dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins GPR32Opnd:$rd); dag InOperandList = (ins GPR32Opnd:$rd);
string AsmString = !strconcat("rdpgpr", "\t$rt, $rd"); string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
InstrItinClass Itinerary = II_RDPGPR; InstrItinClass Itinerary = II_RDPGPR;
▲ Show 20 Lines • Show All 589 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td

Show First 20 Lines • Show All 594 Lines • ▼ Show 20 Linesclass SYNC_FM_MM : MMArch {
let Inst{31-26} = 0x00; let Inst{31-26} = 0x00;
let Inst{25-21} = 0x0; let Inst{25-21} = 0x0;
let Inst{20-16} = stype; let Inst{20-16} = stype;
let Inst{15-6} = 0x1ad; let Inst{15-6} = 0x1ad;
let Inst{5-0} = 0x3c; let Inst{5-0} = 0x3c;
} }
class SYNCI_FM_MM : MMArch { class SYNCI_FM_MM : MMArch {
bits<5> rs; bits<21> addr;
bits<16> offset; bits<5> rs = addr{20-16};
bits<16> offset = addr{15-0};
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0b010000; let Inst{31-26} = 0b010000;
let Inst{25-21} = 0b10000; let Inst{25-21} = 0b10000;
let Inst{20-16} = rs; let Inst{20-16} = rs;
let Inst{15-0} = offset; let Inst{15-0} = offset;
} }
▲ Show 20 Lines • Show All 442 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Linesdef mem_mm_12 : Operand<i32> {
let ParserMatchClass = MipsMemAsmOperand; let ParserMatchClass = MipsMemAsmOperand;
let OperandType = "OPERAND_MEMORY"; let OperandType = "OPERAND_MEMORY";
} }
def mem_mm_16 : Operand<i32> { def mem_mm_16 : Operand<i32> {
let PrintMethod = "printMemOperand"; let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops ptr_rc, simm16); let MIOperandInfo = (ops ptr_rc, simm16);
let EncoderMethod = "getMemEncodingMMImm16"; let EncoderMethod = "getMemEncodingMMImm16";
let DecoderMethod = "DecodeMemMMImm16";
let ParserMatchClass = MipsMemSimm16AsmOperand; let ParserMatchClass = MipsMemSimm16AsmOperand;
let OperandType = "OPERAND_MEMORY"; let OperandType = "OPERAND_MEMORY";
} }
def MipsMemUimm4AsmOperand : AsmOperandClass { def MipsMemUimm4AsmOperand : AsmOperandClass {
let Name = "MemOffsetUimm4"; let Name = "MemOffsetUimm4";
let SuperClasses = [MipsMemAsmOperand]; let SuperClasses = [MipsMemAsmOperand];
let RenderMethod = "addMemOperands"; let RenderMethod = "addMemOperands";
▲ Show 20 Lines • Show All 816 Lines • ▼ Show 20 Lineslet DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
/// Branch Instructions - Short Delay Slot /// Branch Instructions - Short Delay Slot
def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm, def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
GPR32Opnd>, BGEZAL_FM_MM<0x13>; GPR32Opnd>, BGEZAL_FM_MM<0x13>;
def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm, def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
GPR32Opnd>, BGEZAL_FM_MM<0x11>; GPR32Opnd>, BGEZAL_FM_MM<0x11>;
} }
def B_MM : UncondBranch<BEQ_MM, brtarget_mm>, IsBranch, ISA_MICROMIPS; def B_MM : UncondBranch<BEQ_MM, brtarget_mm>, IsBranch, ISA_MICROMIPS;
let DecoderNamespace = "MicroMips" in { let DecoderNamespace = "MicroMips" in {
let Predicates = [InMicroMips] in {
/// Control Instructions /// Control Instructions
def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM; def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM, ISA_MICROMIPS;
def SYNCI_MM : MMRel, SYNCI_FT<"synci">, SYNCI_FM_MM; let DecoderMethod = "DecodeSyncI_MM" in
def SYNCI_MM : MMRel, SYNCI_FT<"synci", mem_mm_16>, SYNCI_FM_MM,
ISA_MICROMIPS32_NOT_MIPS32R6;
let Predicates = [InMicroMips] in {
def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM; def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM; def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM;
def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM; def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>; def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>;
def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>; def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>;
def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>, def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>,
ISA_MIPS32R2; ISA_MIPS32R2;
def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>, def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>,
▲ Show 20 Lines • Show All 241 Lines • ▼ Show 20 Lineslet Predicates = [InMicroMips] in {
def : MipsInstAlias<"sra $rd, $shamt", def : MipsInstAlias<"sra $rd, $shamt",
(SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
def : MipsInstAlias<"srl $rd, $shamt", def : MipsInstAlias<"srl $rd, $shamt",
(SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
def : MipsInstAlias<"rotr $rt, $imm", def : MipsInstAlias<"rotr $rt, $imm",
(ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>; (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>; def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
def : MipsInstAlias<"sync", (SYNC_MM 0), 1>, ISA_MICROMIPS;
defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>, ISA_MICROMIPS; defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>, ISA_MICROMIPS;
defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>, ISA_MICROMIPS; defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>, ISA_MICROMIPS;
defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi_MM>, ISA_MICROMIPS; defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi_MM>, ISA_MICROMIPS;
defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi_MM>, ISA_MICROMIPS; defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi_MM>, ISA_MICROMIPS;
Show All 23 Lines

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 1,651 Lines • ▼ Show 20 Lines InstSE<(outs RO:$rt), (ins),
!strconcat(opstr, "\t$rt"), [], itin, FrmOther, opstr>; !strconcat(opstr, "\t$rt"), [], itin, FrmOther, opstr>;
// Sync // Sync
let hasSideEffects = 1 in let hasSideEffects = 1 in
class SYNC_FT<string opstr> : class SYNC_FT<string opstr> :
InstSE<(outs), (ins uimm5:$stype), "sync $stype", InstSE<(outs), (ins uimm5:$stype), "sync $stype",
[(MipsSync immZExt5:$stype)], II_SYNC, FrmOther, opstr>; [(MipsSync immZExt5:$stype)], II_SYNC, FrmOther, opstr>;
class SYNCI_FT<string opstr> : class SYNCI_FT<string opstr, DAGOperand MO> :
InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [], InstSE<(outs), (ins MO:$addr), !strconcat(opstr, "\t$addr"), [],
II_SYNCI, FrmOther, opstr> { II_SYNCI, FrmOther, opstr> {
let hasSideEffects = 1; let hasSideEffects = 1;
let DecoderMethod = "DecodeSyncI"; let DecoderMethod = "DecodeSyncI";
} }
let hasSideEffects = 1, isCTI = 1 in { let hasSideEffects = 1, isCTI = 1 in {
class TEQ_FT<string opstr, RegisterOperand RO, Operand ImmOp, class TEQ_FT<string opstr, RegisterOperand RO, Operand ImmOp,
InstrItinClass itin = NoItinerary> : InstrItinClass itin = NoItinerary> :
▲ Show 20 Lines • Show All 375 Lines • ▼ Show 20 Lines def SWC3 : SW_FT3<"swc3", COP3Opnd, II_SWC3, store>, LW_FM<0x3b>,
ISA_MIPS1_NOT_32R6_64R6, NOT_ASE_CNMIPS; ISA_MIPS1_NOT_32R6_64R6, NOT_ASE_CNMIPS;
def LDC3 : LW_FT3<"ldc3", COP3Opnd, II_LDC3, load>, LW_FM<0x37>, def LDC3 : LW_FT3<"ldc3", COP3Opnd, II_LDC3, load>, LW_FM<0x37>,
ISA_MIPS2, NOT_ASE_CNMIPS; ISA_MIPS2, NOT_ASE_CNMIPS;
def SDC3 : SW_FT3<"sdc3", COP3Opnd, II_SDC3, store>, LW_FM<0x3f>, def SDC3 : SW_FT3<"sdc3", COP3Opnd, II_SDC3, store>, LW_FM<0x3f>,
ISA_MIPS2, NOT_ASE_CNMIPS; ISA_MIPS2, NOT_ASE_CNMIPS;
} }
def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2; def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2;
def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2; def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci", mem_simm16>, SYNCI_FM,
ISA_MIPS32R2;
} }
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>, def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>,
ISA_MIPS2; ISA_MIPS2;
def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10, II_TGE>, TEQ_FM<0x30>, def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10, II_TGE>, TEQ_FM<0x30>,
ISA_MIPS2; ISA_MIPS2;
def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10, II_TGEU>, TEQ_FM<0x31>, def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10, II_TGEU>, TEQ_FM<0x31>,
▲ Show 20 Lines • Show All 574 Lines • ▼ Show 20 Lineslet AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"srl $rd, $rt", def : MipsInstAlias<"srl $rd, $rt",
(SRLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; (SRLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
def : MipsInstAlias<"seh $rd", (SEH GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, def : MipsInstAlias<"seh $rd", (SEH GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
ISA_MIPS32R2; ISA_MIPS32R2;
def : MipsInstAlias<"seb $rd", (SEB GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, def : MipsInstAlias<"seb $rd", (SEB GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
ISA_MIPS32R2; ISA_MIPS32R2;
} }
def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6; def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
def : MipsInstAlias<"sync", let AdditionalPredicates = [NotInMicroMips] in
(SYNC 0), 1>, ISA_MIPS2; def : MipsInstAlias<"sync", (SYNC 0), 1>, ISA_MIPS2;
def : MipsInstAlias<"mulo $rs, $rt", def : MipsInstAlias<"mulo $rs, $rt",
(MULOMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, (MULOMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"mulou $rs, $rt", def : MipsInstAlias<"mulou $rs, $rt",
(MULOUMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, (MULOUMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
▲ Show 20 Lines • Show All 456 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

Show First 20 Lines • Show All 218 Lines • ▼ Show 20 Lines
0x82 0x54 0xb0 0x01 # CHECK: mul.d $f0, $f2, $f4 0x82 0x54 0xb0 0x01 # CHECK: mul.d $f0, $f2, $f4
0x82 0x54 0xf0 0x01 # CHECK: div.d $f0, $f2, $f4 0x82 0x54 0xf0 0x01 # CHECK: div.d $f0, $f2, $f4
0x02 0x54 0x7b 0x20 # CHECK: mov.d $f0, $f2 0x02 0x54 0x7b 0x20 # CHECK: mov.d $f0, $f2
0x02 0x54 0x7b 0x2b # CHECK: neg.d $f0, $f2 0x02 0x54 0x7b 0x2b # CHECK: neg.d $f0, $f2
0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2 0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2
0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2 0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2
0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2 0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2
0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2 0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2
0x07 0x00 0x7c 0x6b # CHECK: sync 7
0x03 0x42 0x00 0x04 # CHECK: synci 1024($3)

llvm/trunk/test/MC/Mips/micromips/valid.s

Show First 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
bc1t 8 # CHECK: bc1t 8 # encoding: [0x43,0xa0,0x00,0x04] bc1t 8 # CHECK: bc1t 8 # encoding: [0x43,0xa0,0x00,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1T_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1T_MM
bc1f 16 # CHECK: bc1f 16 # encoding: [0x43,0x80,0x00,0x08] bc1f 16 # CHECK: bc1f 16 # encoding: [0x43,0x80,0x00,0x08]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1F_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1F_MM
bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x43,0xa4,0x00,0x02] bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x43,0xa4,0x00,0x02]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1T_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1T_MM
bc1f $fcc2, -20 # CHECK: bc1f $fcc2, -20 # encoding: [0x43,0x88,0xff,0xf6] bc1f $fcc2, -20 # CHECK: bc1f $fcc2, -20 # encoding: [0x43,0x88,0xff,0xf6]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1F_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1F_MM
sync # CHECK: sync # encoding: [0x00,0x00,0x6b,0x7c] sync # CHECK: sync # encoding: [0x00,0x00,0x6b,0x7c]
sync 0 # CHECK: sync 0 # encoding: [0x00,0x00,0x6b,0x7c] # CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC_MM
sync 0 # CHECK: sync # encoding: [0x00,0x00,0x6b,0x7c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC_MM
sync 1 # CHECK: sync 1 # encoding: [0x00,0x01,0x6b,0x7c] sync 1 # CHECK: sync 1 # encoding: [0x00,0x01,0x6b,0x7c]
synci 64($5) # CHECK: synci 64($5) # encoding: [0x42,0x00,0x00,0x40] # CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC_MM
synci 64($5) # CHECK: synci 64($5) # encoding: [0x42,0x05,0x00,0x40]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI_MM

llvm/trunk/test/MC/Mips/mips32r2/valid.s

Show First 20 Lines • Show All 277 Lines • ▼ Show 20 Linesa:
suxc1 $f12,$k1($13) suxc1 $f12,$k1($13)
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
#!CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
#!CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5, $7, 620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teq $5, $7, 620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0] teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0]
tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5, $19, 340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tge $5, $19, 340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $17, 5025 # CHECK: tgei $17, 5025 # encoding: [0x06,0x28,0x13,0xa1] tgei $17, 5025 # CHECK: tgei $17, 5025 # encoding: [0x06,0x28,0x13,0xa1]
Show All 23 Linesa:
tnei $12, -29647 # CHECK: tnei $12, -29647 # encoding: [0x05,0x8e,0x8c,0x31] tnei $12, -29647 # CHECK: tnei $12, -29647 # encoding: [0x05,0x8e,0x8c,0x31]
trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d] trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d]
trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d] trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d] trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d] trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
wsbh $k1,$9 wsbh $k1,$9
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e] synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
#!CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI
1: 1:
# Check that we accept traditional %relocation(symbol) offsets for stores # Check that we accept traditional %relocation(symbol) offsets for stores
# and loads, not just a sign 16 bit offset. # and loads, not just a sign 16 bit offset.
lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A] lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A]
lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A] lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A]
Show All 18 Lines

llvm/trunk/test/MC/Mips/mips32r3/valid.s

Show First 20 Lines • Show All 277 Lines • ▼ Show 20 Linesa:
suxc1 $f12,$k1($13) suxc1 $f12,$k1($13)
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5, $7, 620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teq $5, $7, 620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0] teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0]
tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5, $19, 340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tge $5, $19, 340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $17, 5025 # CHECK: tgei $17, 5025 # encoding: [0x06,0x28,0x13,0xa1] tgei $17, 5025 # CHECK: tgei $17, 5025 # encoding: [0x06,0x28,0x13,0xa1]
Show All 23 Linesa:
tnei $12, -29647 # CHECK: tnei $12, -29647 # encoding: [0x05,0x8e,0x8c,0x31] tnei $12, -29647 # CHECK: tnei $12, -29647 # encoding: [0x05,0x8e,0x8c,0x31]
trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d] trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d]
trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d] trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d] trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d] trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
wsbh $k1,$9 wsbh $k1,$9
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e] synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI
1: 1:
# Check that we accept traditional %relocation(symbol) offsets for stores # Check that we accept traditional %relocation(symbol) offsets for stores
# and loads, not just a sign 16 bit offset. # and loads, not just a sign 16 bit offset.
lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A] lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A]
lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A] lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A]
Show All 18 Lines

llvm/trunk/test/MC/Mips/mips32r5/valid.s

Show First 20 Lines • Show All 278 Lines • ▼ Show 20 Linesa:
suxc1 $f12,$k1($13) suxc1 $f12,$k1($13)
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5, $7, 620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teq $5, $7, 620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0] teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0]
tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5, $19, 340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tge $5, $19, 340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $17, 5025 # CHECK: tgei $17, 5025 # encoding: [0x06,0x28,0x13,0xa1] tgei $17, 5025 # CHECK: tgei $17, 5025 # encoding: [0x06,0x28,0x13,0xa1]
Show All 24 Linesa:
trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d] trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d]
trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d] trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d] trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d] trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
wsbh $k1,$9 wsbh $k1,$9
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e] synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI
1: 1:
# Check that we accept traditional %relocation(symbol) offsets for stores # Check that we accept traditional %relocation(symbol) offsets for stores
# and loads, not just a sign 16 bit offset. # and loads, not just a sign 16 bit offset.
lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A] lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A]
lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A] lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A]
Show All 18 Lines

llvm/trunk/test/MC/Mips/mips32r6/valid.s

Show First 20 Lines • Show All 214 Lines • ▼ Show 20 Linesa:
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e] sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
# CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
Show All 11 Linesa:
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI
1: 1:
# Check that we accept traditional %relocation(symbol) offsets for stores # Check that we accept traditional %relocation(symbol) offsets for stores
# and loads, not just a sign 16 bit offset. # and loads, not just a sign 16 bit offset.
lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A] lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A]
lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A] lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A]
Show All 13 Lines

llvm/trunk/test/MC/Mips/mips64r2/valid.s

Show First 20 Lines • Show All 344 Lines • ▼ Show 20 Linesa:
suxc1 $f12,$k1($13) suxc1 $f12,$k1($13)
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5, $7, 620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teq $5, $7, 620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0] teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0]
tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5, $19, 340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tge $5, $19, 340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $17, 5025 # CHECK: tgei $17, 5025 # encoding: [0x06,0x28,0x13,0xa1] tgei $17, 5025 # CHECK: tgei $17, 5025 # encoding: [0x06,0x28,0x13,0xa1]
Show All 25 Linesa:
trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09] trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d] trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d] trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d] trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d] trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9 wsbh $k1,$9
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
1: 1:
# Check that we accept traditional %relocation(symbol) offsets for stores # Check that we accept traditional %relocation(symbol) offsets for stores
# and loads, not just a sign 16 bit offset. # and loads, not just a sign 16 bit offset.
lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A] lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A]
lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A] lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A]
Show All 26 Lines

llvm/trunk/test/MC/Mips/mips64r3/valid.s

Show First 20 Lines • Show All 331 Lines • ▼ Show 20 Linesa:
suxc1 $f12,$k1($13) suxc1 $f12,$k1($13)
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5, $7, 620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teq $5, $7, 620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0] teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0]
tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5, $19, 340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tge $5, $19, 340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $17, 5025 # CHECK: tgei $17, 5025 # encoding: [0x06,0x28,0x13,0xa1] tgei $17, 5025 # CHECK: tgei $17, 5025 # encoding: [0x06,0x28,0x13,0xa1]
Show All 25 Linesa:
trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09] trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d] trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d] trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d] trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d] trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9 wsbh $k1,$9
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI
1: 1:
# Check that we accept traditional %relocation(symbol) offsets for stores # Check that we accept traditional %relocation(symbol) offsets for stores
# and loads, not just a sign 16 bit offset. # and loads, not just a sign 16 bit offset.
lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A] lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A]
lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A] lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A]
Show All 25 Lines

llvm/trunk/test/MC/Mips/mips64r5/valid.s

Show First 20 Lines • Show All 339 Lines • ▼ Show 20 Linesa:
suxc1 $f12,$k1($13) suxc1 $f12,$k1($13)
sw $ra,-10160($sp) sw $ra,-10160($sp)
swc1 $f6,-8465($24) swc1 $f6,-8465($24)
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5, $7, 620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teq $5, $7, 620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0] teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0]
tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5, $19, 340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tge $5, $19, 340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $17, 5025 # CHECK: tgei $17, 5025 # encoding: [0x06,0x28,0x13,0xa1] tgei $17, 5025 # CHECK: tgei $17, 5025 # encoding: [0x06,0x28,0x13,0xa1]
Show All 25 Linesa:
trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09] trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d] trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d] trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d] trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d] trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9 wsbh $k1,$9
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI
1: 1:
# Check that we accept traditional %relocation(symbol) offsets for stores # Check that we accept traditional %relocation(symbol) offsets for stores
# and loads, not just a sign 16 bit offset. # and loads, not just a sign 16 bit offset.
lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A] lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A]
lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A] lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A]
Show All 25 Lines

llvm/trunk/test/MC/Mips/mips64r6/valid.s

Show First 20 Lines • Show All 248 Lines • ▼ Show 20 Linesa:
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b] sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04] sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07] sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06] srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction
swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30] swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30]
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
# CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
Show All 11 Linesa:
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNCI
1: 1:
# Check that we accept traditional %relocation(symbol) offsets for stores # Check that we accept traditional %relocation(symbol) offsets for stores
# and loads, not just a sign 16 bit offset. # and loads, not just a sign 16 bit offset.
lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A] lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A]
lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A] lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A]
lh $3, %lo(g_8)($2) # CHECK: encoding: [0x84,0x43,A,A] lh $3, %lo(g_8)($2) # CHECK: encoding: [0x84,0x43,A,A]
Show All 15 Lines