[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word

[lei]

Summary

Legalize and emit code for:

• xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word
• xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word

[lei]

remove excess code.

[nemanjai]

lib/Target/PowerPC/PPCISelLowering.cpp

12286 ↗

(On Diff #142678)

Can we just add a condition to the check below rather than repeating most of the condition? You can even just fold the two type checks into another Boolean variable similar to ValidTypeForStoreFltAsInt. Furthermore, you can sink the check for the input types into the condition and exit early to prevent having to go through all the subsequent checks.

lib/Target/PowerPC/PPCInstrVSX.td

2527

Can you please move the anonymous patterns to a separate section from the instruction defs?

test/CodeGen/PowerPC/f128-truncateNconv.ll

2–3

I missed this on the initial review, please add -verify-machineinstrs.

[lei]

Rebased with Unify handling for conversion of FP_TO_INT feeding a store (https://reviews.llvm.org/D46102).

[nemanjai]

LGTM.

lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400, Predicates = [HasP9Vector] in {
 
   // Round & Convert QP -> DP (dword[1] is set to zero)
   def XSCVQPDP  : X_VT5_XO5_VB5   <63, 20, 836, "xscvqpdp" , []>;
   def XSCVQPDPO : X_VT5_XO5_VB5_Ro<63, 20, 836, "xscvqpdpo", []>;
 
   // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
   def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>;
   def XSCVQPSWZ : X_VT5_XO5_VB5<63,  9, 836, "xscvqpswz", []>;
   def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>;
   def XSCVQPUWZ : X_VT5_XO5_VB5<63,  1, 836, "xscvqpuwz", []>;
 
   // Convert (Un)Signed DWord -> QP.
   def XSCVSDQP  : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>;
   def : Pat<(f128 (sint_to_fp i64:$src)),
             (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
   def XSCVUDQP  : X_VT5_XO5_VB5_TyVB<63,  2, 836, "xscvudqp", vfrc, []>;
   def : Pat<(f128 (uint_to_fp i64:$src)),
let AddedComplexity = 400, Predicates = [HasP9Vector] in {
 
   // Convert Unsigned Byte in memory -> QP
   def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi8)),
             (f128 (XSCVUDQP (LXSIBZX xoaddr:$src)))>;
 
   // Truncate & Convert QP -> (Un)Signed (D)Word.
   def : Pat<(i64 (fp_to_sint f128:$src)), (i64 (MFVRD (XSCVQPSDZ $src)))>;
   def : Pat<(i64 (fp_to_uint f128:$src)), (i64 (MFVRD (XSCVQPUDZ $src)))>;
+  def : Pat<(i32 (fp_to_sint f128:$src)),
+            (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC)))>;
+  def : Pat<(i32 (fp_to_uint f128:$src)),
+            (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC)))>;
 
   // Instructions for fptosint (i64,i16,i8) feeding a store.
   def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), xaddr:$dst, 8),
             (STXSDX (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC),
                     xaddr:$dst)>;
   def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), ixaddr:$dst, 8),
             (STXSD (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC),
                    ixaddr:$dst)>;
   def : Pat<(PPCstore_scal_int_from_vsr
+              (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), xoaddr:$dst, 4),
+            (STXSIWX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), xoaddr:$dst)>;
+  def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xaddr:$dst, 8),
             (STXSDX (XSCVDPSXDS f64:$src), xaddr:$dst)>;
   def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), ixaddr:$dst, 8),
             (STXSD (XSCVDPSXDS f64:$src), ixaddr:$dst)>;
   def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xoaddr:$dst, 2),
             (STXSIHX (XSCVDPSXWS f64:$src), xoaddr:$dst)>;
   def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xoaddr:$dst, 1),
             (STXSIBX (XSCVDPSXWS f64:$src), xoaddr:$dst)>;
 
   // Instructions for fptouint (i64,i16,i8) feeding a store.
   def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xaddr:$dst, 8),
             (STXSDX (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
                     xaddr:$dst)>;
   def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), ixaddr:$dst, 8),
             (STXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
                    ixaddr:$dst)>;
   def : Pat<(PPCstore_scal_int_from_vsr
+              (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xoaddr:$dst, 4),
+            (STXSIWX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), xoaddr:$dst)>;
+  def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xaddr:$dst, 8),
             (STXSDX (XSCVDPUXDS f64:$src), xaddr:$dst)>;
   def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), ixaddr:$dst, 8),
             (STXSD (XSCVDPUXDS f64:$src), ixaddr:$dst)>;
   def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 2),
             (STXSIHX (XSCVDPUXWS f64:$src), xoaddr:$dst)>;

test/CodeGen/PowerPC/f128-truncateNconv.ll

 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -verify-machineinstrs -enable-ppc-quad-precision \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s
 
 @f128Array = global [4 x fp128] [fp128 0xL00000000000000004004C00000000000,
                                  fp128 0xLF000000000000000400808AB851EB851,
                                  fp128 0xL5000000000000000400E0C26324C8366,
                                  fp128 0xL8000000000000000400A24E2E147AE14],
                                 align 16
 
 ; Function Attrs: norecurse nounwind readonly
entry:
   store i64 %conv, i64* %arrayidx, align 8
   ret void
 
 ; CHECK-LABEL: qpConv2udw_testXForm
 ; CHECK: xscvqpudz [[CONV:[0-9]+]],
 ; CHECK-NEXT: stxsdx [[CONV]], 3, 4
 ; CHECK-NEXT: blr
 }
+
+; Function Attrs: norecurse nounwind readonly
+define signext i32 @qpConv2sw(fp128* nocapture readonly %a)  {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %conv = fptosi fp128 %0 to i32
+  ret i32 %conv
+
+; CHECK-LABEL: qpConv2sw
+; CHECK: lxv [[REG:[0-9]+]], 0(3)
+; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[REG]]
+; CHECK-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
+; CHECK-NEXT: extsw 3, [[REG2]]
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2sw_02(i32* nocapture %res) {
+entry:
+  %0 = load fp128, fp128* getelementptr inbounds
+                            ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
+                             i64 2), align 16
+  %conv = fptosi fp128 %0 to i32
+  store i32 %conv, i32* %res, align 4
+  ret void
+
+; CHECK-LABEL: qpConv2sw_02
+; CHECK: addis [[REG0:[0-9]+]], 2, .LC0@toc@ha
+; CHECK: ld [[REG0]], .LC0@toc@l([[REG0]])
+; CHECK: lxv [[REG:[0-9]+]], 32([[REG0]])
+; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[REG]]
+; CHECK-NEXT: stxsiwx [[CONV]], 0, 3
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readonly
+define signext i32 @qpConv2sw_03(fp128* nocapture readonly %a)  {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %1 = load fp128, fp128* getelementptr inbounds
+                            ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
+                             i64 1), align 16
+  %add = fadd fp128 %0, %1
+  %conv = fptosi fp128 %add to i32
+  ret i32 %conv
+
+; CHECK-LABEL: qpConv2sw_03
+; CHECK: addis [[REG0:[0-9]+]], 2, .LC0@toc@ha
+; CHECK-DAG: ld [[REG0]], .LC0@toc@l([[REG0]])
+; CHECK-DAG: lxv [[REG1:[0-9]+]], 16([[REG0]])
+; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
+; CHECK-NEXT: xsaddqp [[ADD:[0-9]+]], [[REG]], [[REG1]]
+; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[ADD]]
+; CHECK-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
+; CHECK-NEXT: extsw 3, [[REG2]]
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2sw_04(fp128* nocapture readonly %a,
+                          fp128* nocapture readonly %b, i32* nocapture %res) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %1 = load fp128, fp128* %b, align 16
+  %add = fadd fp128 %0, %1
+  %conv = fptosi fp128 %add to i32
+  store i32 %conv, i32* %res, align 4
+  ret void
+
+; CHECK-LABEL: qpConv2sw_04
+; CHECK-DAG: lxv [[REG1:[0-9]+]], 0(4)
+; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
+; CHECK-NEXT: xsaddqp [[ADD:[0-9]+]], [[REG]], [[REG1]]
+; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[ADD]]
+; CHECK-NEXT: stxsiwx [[CONV]], 0, 5
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readonly
+define zeroext i32 @qpConv2uw(fp128* nocapture readonly %a)  {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %conv = fptoui fp128 %0 to i32
+  ret i32 %conv
+
+; CHECK-LABEL: qpConv2uw
+; CHECK: lxv [[REG:[0-9]+]], 0(3)
+; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[ADD]]
+; CHECK-NEXT: mfvsrwz 3, [[CONV]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2uw_02(i32* nocapture %res) {
+entry:
+  %0 = load fp128, fp128* getelementptr inbounds
+                            ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
+                             i64 2), align 16
+  %conv = fptoui fp128 %0 to i32
+  store i32 %conv, i32* %res, align 4
+  ret void
+
+; CHECK-LABEL: qpConv2uw_02
+; CHECK: addis [[REG0:[0-9]+]], 2, .LC0@toc@ha
+; CHECK: ld [[REG0]], .LC0@toc@l([[REG0]])
+; CHECK: lxv [[REG:[0-9]+]], 32([[REG0]])
+; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[ADD]]
+; CHECK-NEXT: stxsiwx [[CONV]], 0, 3
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readonly
+define zeroext i32 @qpConv2uw_03(fp128* nocapture readonly %a)  {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %1 = load fp128, fp128* getelementptr inbounds
+                            ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
+                             i64 1), align 16
+  %add = fadd fp128 %0, %1
+  %conv = fptoui fp128 %add to i32
+  ret i32 %conv
+
+; CHECK-LABEL: qpConv2uw_03
+; CHECK: addis [[REG0:[0-9]+]], 2, .LC0@toc@ha
+; CHECK-DAG: ld [[REG0]], .LC0@toc@l([[REG0]])
+; CHECK-DAG: lxv [[REG1:[0-9]+]], 16([[REG0]])
+; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
+; CHECK-NEXT: xsaddqp [[ADD:[0-9]+]], [[REG]], [[REG1]]
+; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[ADD]]
+; CHECK-NEXT: mfvsrwz 3, [[CONV]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2uw_04(fp128* nocapture readonly %a,
+                          fp128* nocapture readonly %b, i32* nocapture %res) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %1 = load fp128, fp128* %b, align 16
+  %add = fadd fp128 %0, %1
+  %conv = fptoui fp128 %add to i32
+  store i32 %conv, i32* %res, align 4
+  ret void
+
+; CHECK-LABEL: qpConv2uw_04
+; CHECK-DAG: lxv [[REG1:[0-9]+]], 0(4)
+; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
+; CHECK-NEXT: xsaddqp [[ADD:[0-9]+]], [[REG]], [[REG1]]
+; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[ADD]]
+; CHECK-NEXT: stxsiwx [[CONV]], 0, 5
+; CHECK: blr
+}