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[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word
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Authored by lei on Apr 13 2018, 2:19 PM.

Details

Summary

Legalize and emit code for:

  • xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word
  • xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word

Diff Detail

Event Timeline

lei created this revision.Apr 13 2018, 2:19 PM
lei updated this revision to Diff 142678.Apr 16 2018, 12:36 PM

remove excess code.

nemanjai added inline comments.Apr 17 2018, 6:05 PM
lib/Target/PowerPC/PPCISelLowering.cpp
12286

Can we just add a condition to the check below rather than repeating most of the condition? You can even just fold the two type checks into another Boolean variable similar to ValidTypeForStoreFltAsInt. Furthermore, you can sink the check for the input types into the condition and exit early to prevent having to go through all the subsequent checks.

lib/Target/PowerPC/PPCInstrVSX.td
2515

Can you please move the anonymous patterns to a separate section from the instruction defs?

test/CodeGen/PowerPC/f128-truncateNconv.ll
2

I missed this on the initial review, please add -verify-machineinstrs.

lei updated this revision to Diff 144064.Apr 25 2018, 10:56 PM

Rebased with Unify handling for conversion of FP_TO_INT feeding a store (https://reviews.llvm.org/D46102).

nemanjai accepted this revision.May 7 2018, 7:26 PM

LGTM.

This revision is now accepted and ready to land.May 7 2018, 7:26 PM
This revision was automatically updated to reflect the committed changes.