This is an archive of the discontinued LLVM Phabricator instance.

[X86] Add FP logical scheduler class
ClosedPublic

Authored by RKSimon on Apr 13 2018, 10:14 AM.

Details

Summary

Split the fp and integer vector logical instruction scheduler classes - older CPUs especially often handled these on different pipes.

This unearthed a couple of things that are also handled in this patch (I can split these off if people wish):

(1) we were tagging avx512 fp logic ops as WriteFAdd, probably because of the lack of WriteFLogic
(2) SandyBridge had integer logic ops only using Port5, when afaict they can use Ports015.
(3) Cleaned up x86 FCHS/FABS scheduling as they are typically treated as fp logic ops.

Diff Detail

Repository
rL LLVM

Event Timeline

RKSimon created this revision.Apr 13 2018, 10:14 AM
craig.topper added inline comments.Apr 15 2018, 6:14 PM
lib/Target/X86/X86InstrFPStack.td
312

These look to be even more restricted than regular FP logic. For instance skylake only has them on port0 even though the xmm versions are on 3 ports. Agner's data shows them with 2 cyc latency and throughput on Jaguar. Should they be their own class?

RKSimon updated this revision to Diff 143096.Apr 19 2018, 8:01 AM

Split off x87 fabs/fchs instructions into WriteFSign class as well

This revision is now accepted and ready to land.Apr 20 2018, 10:53 AM
This revision was automatically updated to reflect the committed changes.