Split the fp and integer vector logical instruction scheduler classes - older CPUs especially often handled these on different pipes.
This unearthed a couple of things that are also handled in this patch (I can split these off if people wish):
(1) we were tagging avx512 fp logic ops as WriteFAdd, probably because of the lack of WriteFLogic
(2) SandyBridge had integer logic ops only using Port5, when afaict they can use Ports015.
(3) Cleaned up x86 FCHS/FABS scheduling as they are typically treated as fp logic ops.
These look to be even more restricted than regular FP logic. For instance skylake only has them on port0 even though the xmm versions are on 3 ports. Agner's data shows them with 2 cyc latency and throughput on Jaguar. Should they be their own class?