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[RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC
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Authored by kito-cheng on Apr 12 2018, 2:04 AM.

Details

Summary

According RISC-V ELF psABI specification, base RV32 and RV64 ISAs only allow 32-bit instruction alignment, but allow to be aligned to 16-bit boundaries for C-extension.

So we just align to 4 bytes and 2 bytes for C-extension is enough.

Diff Detail

Repository
rL LLVM

Event Timeline

kito-cheng created this revision.Apr 12 2018, 2:04 AM

Changes:

  • Add test case.
asb accepted this revision.Apr 12 2018, 2:31 AM

Thanks Kito, looks good to me.

This revision is now accepted and ready to land.Apr 12 2018, 2:31 AM
This revision was automatically updated to reflect the committed changes.