[X86] Add SchedWrites for CMOV and SETCC. Use them to remove InstRWs.

[craig.topper]

Summary

Cmov and setcc previously used WriteALU, but on Intel processors at least they are more restricted than basic ALU ops.

This patch adds new SchedWrites for them and removes the InstRWs. I had to leave some InstRWs for CMOVA/CMOVBE and SETA/SETBE because those have an extra uop relative to the other condition codes on Intel CPUs.

[RKSimon]

lib/Target/X86/X86ScheduleBtVer2.td

145

Move the WriteSETCCStore def into the models so we don't get the regression on btver2 tests?

[craig.topper]

lib/Target/X86/X86ScheduleBtVer2.td

145

You mean make it a regular SchedWrite and not a WriteSequence?

[RKSimon]

lib/Target/X86/X86ScheduleBtVer2.td

145

If you can, otherwise please can you add a InstRW like znver1 has to btver2?

[craig.topper]

Use SchedWrite instead of SchedWriteSequence. Avoid all test changes by matching previous behavior for SLM and BTVER2. Add a few FIXMEs.

[RKSimon]

Thanks - LGTM as an NFC - I guess the ryzen fixme can stay for now if @GGanesh doesn't get back in time.

lib/Target/X86/X86ScheduleZnver1.td

617

@craig.topper You can probably fold this into the WriteSETCC declarations above and move the FIXME question there.

@GGanesh shouldn't this have a ZnAGU dependency?

[GGanesh]

lib/Target/X86/X86ScheduleZnver1.td

617

Yes all memory instructions have dependency with address generation unit!

lib/Target/X86/X86InstrCMovSetCC.td

 // instructions.
 //
 //===----------------------------------------------------------------------===//
 
 
 // CMOV instructions.
 multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
   let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
-      isCommutable = 1, SchedRW = [WriteALU] in {
+      isCommutable = 1, SchedRW = [WriteCMOV] in {
     def NAME#16rr
       : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
           !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
           [(set GR16:$dst,
                 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))],
                 IIC_CMOV16_RR>, TB, OpSize16;
     def NAME#32rr
       : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
           !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
           [(set GR32:$dst,
                 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
                 IIC_CMOV32_RR>, TB, OpSize32;
     def NAME#64rr
       :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
           !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
           [(set GR64:$dst,
                 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))],
                 IIC_CMOV64_RR>, TB;
   }
 
   let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
-      SchedRW = [WriteALULd, ReadAfterLd] in {
+      SchedRW = [WriteCMOVLd, ReadAfterLd] in {
     def NAME#16rm
       : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
           !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
           [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
                                     CondNode, EFLAGS))], IIC_CMOV16_RM>,
                                     TB, OpSize16;
     def NAME#32rm
       : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),

 
 
 // SetCC instructions.
 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
   let Uses = [EFLAGS] in {
     def r    : I<opc, MRMXr,  (outs GR8:$dst), (ins),
                      !strconcat(Mnemonic, "\t$dst"),
                      [(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
-                     IIC_SET_R>, TB, Sched<[WriteALU]>;
+                     IIC_SET_R>, TB, Sched<[WriteSETCC]>;
     def m    : I<opc, MRMXm,  (outs), (ins i8mem:$dst),
                      !strconcat(Mnemonic, "\t$dst"),
                      [(store (X86setcc OpNode, EFLAGS), addr:$dst)],
-                     IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
+                     IIC_SET_M>, TB, Sched<[WriteSETCCStore]>;
   } // Uses = [EFLAGS]
 }
 
 defm SETO  : SETCC<0x90, "seto",  X86_COND_O>;   // is overflow bit set
 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>;  // is overflow bit not set
 defm SETB  : SETCC<0x92, "setb",  X86_COND_B>;   // unsigned less than
 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>;  // unsigned greater or equal
 defm SETE  : SETCC<0x94, "sete",  X86_COND_E>;   // equal to

lib/Target/X86/X86SchedBroadwell.td

 defm : BWWriteResPair<WriteALU,   [BWPort0156], 1>; // Simple integer ALU op.
 defm : BWWriteResPair<WriteIMul,  [BWPort1],   3>; // Integer multiplication.
 defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
 defm : BWWriteResPair<WriteCRC32, [BWPort1],   3>;
 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 
 def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
 
+defm : BWWriteResPair<WriteCMOV,  [BWPort06], 1>; // Conditional move.
+def  : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
+
 // Bit counts.
 defm : BWWriteResPair<WriteBitScan, [BWPort1], 3>;
 defm : BWWriteResPair<WriteLZCNT,   [BWPort1], 3>;
 defm : BWWriteResPair<WriteTZCNT,   [BWPort1], 3>;
 defm : BWWriteResPair<WritePOPCNT,  [BWPort1], 3>;
 
 // Integer shifts and rotates.
 defm : BWWriteResPair<WriteShift, [BWPort06],  1>;
def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
                                            "BT(16|32|64)ri8",
                                            "BT(16|32|64)rr",
                                            "BTC(16|32|64)ri8",
                                            "BTC(16|32|64)rr",
                                            "BTR(16|32|64)ri8",
                                            "BTR(16|32|64)rr",
                                            "BTS(16|32|64)ri8",
                                            "BTS(16|32|64)rr",
-                                           "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
                                            "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
                                            "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
                                            "JMP_1",
                                            "JMP_4",
                                            "RORX(32|64)ri",
                                            "SAR(8|16|32|64)r1",
                                            "SAR(8|16|32|64)ri",
                                            "SARX(32|64)rr",
                                            "SBB(16|32|64)ri",
                                            "SBB(16|32|64)i",
                                            "SBB(8|16|32|64)rr",
-                                           "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
                                            "SHL(8|16|32|64)r1",
                                            "SHL(8|16|32|64)ri",
                                            "SHLX(32|64)rr",
                                            "SHR(8|16|32|64)r1",
                                            "SHR(8|16|32|64)ri",
                                            "SHRX(32|64)rr")>;
 
 def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {

 
 def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
   let Latency = 2;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>;
 
-def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> {
-  let Latency = 2;
-  let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
-}
-def: InstRW<[BWWriteResGroup23], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
-
 def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
   let Latency = 2;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
 
 def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64",
                                             "JMP(16|32|64)m")>;
 
 def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
   let Latency = 6;
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8",
-                                            "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
                                             "RORX(32|64)mi",
                                             "SARX(32|64)rm",
                                             "SHLX(32|64)rm",
                                             "SHRX(32|64)rm")>;
 def: InstRW<[BWWriteResGroup63, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
                                                       ADCX32rm, ADCX64rm,
                                                       ADOX32rm, ADOX64rm,
                                                       SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;

lib/Target/X86/X86SchedHaswell.td

 
 defm : HWWriteResPair<WriteALU,   [HWPort0156], 1>;
 defm : HWWriteResPair<WriteIMul,  [HWPort1],   3>;
 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
 defm : HWWriteResPair<WriteShift, [HWPort06],  1>;
 defm : HWWriteResPair<WriteJump,  [HWPort06],   1>;
 defm : HWWriteResPair<WriteCRC32, [HWPort1],   3>;
 
+defm : HWWriteResPair<WriteCMOV,  [HWPort06,HWPort0156], 2, [1,1], 2>; // Conditional move.
+def  : WriteRes<WriteSETCC, [HWPort06]>; // Setcc.
+
 // This is for simple LEAs with one or two input operands.
 // The complex ones can only execute on port 1, and they require two cycles on
 // the port to read all inputs. We don't model that.
 def : WriteRes<WriteLEA, [HWPort15]>;
 
 // Bit counts.
 defm : HWWriteResPair<WriteBitScan, [HWPort1], 3>;
 defm : HWWriteResPair<WriteLZCNT,   [HWPort1], 3>;
def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8",
                                            "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
                                            "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
                                            "JMP_1",
                                            "JMP_4",
                                            "RORX(32|64)ri",
                                            "SAR(8|16|32|64)r1",
                                            "SAR(8|16|32|64)ri",
                                            "SARX(32|64)rr",
-                                           "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
                                            "SHL(8|16|32|64)r1",
                                            "SHL(8|16|32|64)ri",
                                            "SHLX(32|64)rr",
                                            "SHR(8|16|32|64)r1",
                                            "SHR(8|16|32|64)ri",
                                            "SHRX(32|64)rr")>;
 
 def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {

 
 def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> {
   let Latency = 2;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup21], (instregex "FNSTCW16m")>;
 
-def HWWriteResGroup22 : SchedWriteRes<[HWPort4,HWPort237,HWPort06]> {
-  let Latency = 2;
-  let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
-}
-def: InstRW<[HWWriteResGroup22], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
-
 def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> {
   let Latency = 2;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
 def: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>;
 
 def HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>;
 def: InstRW<[HWWriteResGroup35], (instregex "ADC(8|16|32|64)ri",
                                             "ADC(8|16|32|64)rr",
                                             "ADC(8|16|32|64)i",
-                                            "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
                                             "SBB(8|16|32|64)ri",
                                             "SBB(8|16|32|64)rr",
                                             "SBB(8|16|32|64)i",
                                             "SET(A|BE)r")>;
 
 def HWWriteResGroup36 : SchedWriteRes<[HWPort5,HWPort23]> {
   let Latency = 8;
   let NumMicroOps = 3;
def: InstRW<[HWWriteResGroup41], (instregex "LRETQ",
                                             "RETL",
                                             "RETQ")>;
 
 def HWWriteResGroup43 : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
   let Latency = 7;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
-def: InstRW<[HWWriteResGroup43], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>;
 def: InstRW<[HWWriteResGroup43, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
                                                       SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;
 
 def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
   let ResourceCycles = [1,1,1,1];
 }

lib/Target/X86/X86SchedSandyBridge.td

 defm : SBWriteResPair<WriteIMul,  [SBPort1],   3>;
 defm : SBWriteResPair<WriteIDiv, [SBPort0, SBDivider], 25, [1, 10]>;
 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
 
 defm : SBWriteResPair<WriteShift, [SBPort05],  1>;
 defm : SBWriteResPair<WriteJump,  [SBPort5],   1>;
 defm : SBWriteResPair<WriteCRC32, [SBPort1],   3, [1], 1, 5>;
 
+defm : SBWriteResPair<WriteCMOV,  [SBPort05,SBPort015], 2, [1,1], 2>; // Conditional move.
+def  : WriteRes<WriteSETCC, [SBPort05]>; // Setcc.
+
 // This is for simple LEAs with one or two input operands.
 // The complex ones can only execute on port 1, and they require two cycles on
 // the port to read all inputs. We don't model that.
 def : WriteRes<WriteLEA, [SBPort15]>;
 
 // Bit counts.
 defm : SBWriteResPair<WriteBitScan, [SBPort1], 3, [1], 1, 5>;
 defm : SBWriteResPair<WriteLZCNT,   [SBPort1], 3, [1], 1, 5>;
def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8",
                                            "BTR(16|32|64)ri8",
                                            "BTR(16|32|64)rr",
                                            "BTS(16|32|64)ri8",
                                            "BTS(16|32|64)rr",
                                            "LAHF",
                                            "SAHF",
                                            "SAR(8|16|32|64)ri",
                                            "SAR(8|16|32|64)r1",
-                                           "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
                                            "SHL(8|16|32|64)ri",
                                            "SHL(8|16|32|64)r1",
                                            "SHR(8|16|32|64)ri",
                                            "SHR(8|16|32|64)r1",
                                            "(V?)BLENDPD(Y?)rri",
                                            "(V?)BLENDPS(Y?)rri",
                                            "VMOVDQA(Y?)rr",
                                            "VMOVDQU(Y?)rr")>;

 def SBWriteResGroup19 : SchedWriteRes<[SBPort05,SBPort015]> {
   let Latency = 2;
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup19], (instregex "ADC(8|16|32|64)ri",
                                             "ADC(8|16|32|64)rr",
                                             "ADC(8|16|32|64)i",
-                                            "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
                                             "SBB(8|16|32|64)ri",
                                             "SBB(8|16|32|64)rr",
                                             "SBB(8|16|32|64)i",
                                             "SHLD(16|32|64)rri8",
                                             "SHRD(16|32|64)rri8")>;
 
 def SBWriteResGroup20 : SchedWriteRes<[SBPort0]> {
   let Latency = 5;

 def SBWriteResGroup37 : SchedWriteRes<[SBPort4,SBPort01,SBPort23]> {
   let Latency = 5;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
 def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPD(Y?)mr",
                                             "VMASKMOVPS(Y?)mr")>;
 
-def SBWriteResGroup38 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
-  let Latency = 2;
-  let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SBWriteResGroup38], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
-
 def SBWriteResGroup39 : SchedWriteRes<[SBPort4,SBPort23,SBPort15]> {
   let Latency = 5;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
 def: InstRW<[SBWriteResGroup39], (instregex "(V?)PEXTRBmr",
                                             "VPEXTRDmr",
                                             "VPEXTRWmr")>;

 }
 def: InstRW<[SBWriteResGroup64], (instregex "FARJMP64")>;
 
 def SBWriteResGroup65 : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> {
   let Latency = 7;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
-def: InstRW<[SBWriteResGroup65], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>;
 def: InstRW<[SBWriteResGroup65, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
                                                       SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;
 
 def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> {
   let Latency = 7;
   let NumMicroOps = 4;
   let ResourceCycles = [1,1,2];
 }

lib/Target/X86/X86SchedSkylakeClient.td

 defm : SKLWriteResPair<WriteALU,   [SKLPort0156], 1>; // Simple integer ALU op.
 defm : SKLWriteResPair<WriteIMul,  [SKLPort1],   3>; // Integer multiplication.
 defm : SKLWriteResPair<WriteIDiv, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>; // Integer division.
 defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>;
 
 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
 
+defm : SKLWriteResPair<WriteCMOV,  [SKLPort06], 1>; // Conditional move.
+def  : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
+
 // Bit counts.
 defm : SKLWriteResPair<WriteBitScan, [SKLPort1], 3>;
 defm : SKLWriteResPair<WriteLZCNT,   [SKLPort1], 3>;
 defm : SKLWriteResPair<WriteTZCNT,   [SKLPort1], 3>;
 defm : SKLWriteResPair<WritePOPCNT,  [SKLPort1], 3>;
 
 // Integer shifts and rotates.
 defm : SKLWriteResPair<WriteShift, [SKLPort06],  1>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri",
                                             "BT(16|32|64)rr",
                                             "BTC(16|32|64)ri8",
                                             "BTC(16|32|64)rr",
                                             "BTR(16|32|64)ri8",
                                             "BTR(16|32|64)rr",
                                             "BTS(16|32|64)ri8",
                                             "BTS(16|32|64)rr",
                                             "CLAC",
-                                            "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
                                             "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
                                             "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
                                             "JMP_1",
                                             "JMP_4",
                                             "RORX(32|64)ri",
                                             "SAR(8|16|32|64)r1",
                                             "SAR(8|16|32|64)ri",
                                             "SARX(32|64)rr",
                                             "SBB(16|32|64)ri",
                                             "SBB(16|32|64)i",
                                             "SBB(8|16|32|64)rr",
-                                            "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
                                             "SHL(8|16|32|64)r1",
                                             "SHL(8|16|32|64)ri",
                                             "SHLX(32|64)rr",
                                             "SHR(8|16|32|64)r1",
                                             "SHR(8|16|32|64)ri",
                                             "SHRX(32|64)rr",
                                             "STAC")>;
 

 
 def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
   let Latency = 2;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup25], (instregex "FNSTCW16m")>;
 
-def SKLWriteResGroup26 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
-  let Latency = 2;
-  let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup26], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
-
 def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
   let Latency = 2;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 
 def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSBrm",
                                              "MMX_PXORirm")>;
 
 def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> {
   let Latency = 6;
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
 def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8",
-                                             "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
                                              "RORX(32|64)mi",
                                              "SARX(32|64)rm",
                                              "SHLX(32|64)rm",
                                              "SHRX(32|64)rm")>;
 def: InstRW<[SKLWriteResGroup74, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
                                                        ADCX32rm, ADCX64rm,
                                                        ADOX32rm, ADOX64rm,
                                                        SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;

lib/Target/X86/X86SchedSkylakeServer.td

 defm : SKXWriteResPair<WriteALU,   [SKXPort0156], 1>; // Simple integer ALU op.
 defm : SKXWriteResPair<WriteIMul,  [SKXPort1],   3>; // Integer multiplication.
 defm : SKXWriteResPair<WriteIDiv, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>; // Integer division.
 defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>;
 
 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
 
+defm : SKXWriteResPair<WriteCMOV,  [SKXPort06], 1>; // Conditional move.
+def  : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
+
 // Integer shifts and rotates.
 defm : SKXWriteResPair<WriteShift, [SKXPort06],  1>;
 
 // Bit counts.
 defm : SKXWriteResPair<WriteBitScan, [SKXPort1], 3>;
 defm : SKXWriteResPair<WriteLZCNT,   [SKXPort1], 3>;
 defm : SKXWriteResPair<WriteTZCNT,   [SKXPort1], 3>;
 defm : SKXWriteResPair<WritePOPCNT,  [SKXPort1], 3>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri",
                                             "BT(16|32|64)rr",
                                             "BTC(16|32|64)ri8",
                                             "BTC(16|32|64)rr",
                                             "BTR(16|32|64)ri8",
                                             "BTR(16|32|64)rr",
                                             "BTS(16|32|64)ri8",
                                             "BTS(16|32|64)rr",
                                             "CLAC",
-                                            "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
                                             "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
                                             "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
                                             "JMP_1",
                                             "JMP_4",
                                             "RORX(32|64)ri",
                                             "SAR(8|16|32|64)r1",
                                             "SAR(8|16|32|64)ri",
                                             "SARX(32|64)rr",
                                             "SBB(16|32|64)ri",
                                             "SBB(16|32|64)i",
                                             "SBB(8|16|32|64)rr",
-                                            "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
                                             "SHL(8|16|32|64)r1",
                                             "SHL(8|16|32|64)ri",
                                             "SHLX(32|64)rr",
                                             "SHR(8|16|32|64)r1",
                                             "SHR(8|16|32|64)ri",
                                             "SHRX(32|64)rr",
                                             "STAC")>;
 

 
 def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {
   let Latency = 2;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup25], (instregex "FNSTCW16m")>;
 
-def SKXWriteResGroup26 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
-  let Latency = 2;
-  let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKXWriteResGroup26], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
-
 def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
   let Latency = 2;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 
 def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PABSBrm",
                                              "MMX_PXORirm")>;
 
 def SKXWriteResGroup78 : SchedWriteRes<[SKXPort23,SKXPort06]> {
   let Latency = 6;
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
 def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8",
-                                             "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
                                              "RORX(32|64)mi",
                                              "SARX(32|64)rm",
                                              "SHLX(32|64)rm",
                                              "SHRX(32|64)rm")>;
 def: InstRW<[SKXWriteResGroup78, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
                                                        ADCX32rm, ADCX64rm,
                                                        ADOX32rm, ADOX64rm,
                                                        SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;

lib/Target/X86/X86Schedule.td

multiclass X86SchedWritePair {
   // Register-Memory operation.
   def Ld : SchedWrite;
   // Register-Register operation.
   def NAME : X86FoldableSchedWrite {
     let Folded = !cast<SchedWrite>(NAME#"Ld");
   }
 }
 
+// Loads, stores, and moves, not folded with other operations.
+def WriteLoad  : SchedWrite;
+def WriteStore : SchedWrite;
+def WriteMove  : SchedWrite;
+
 // Arithmetic.
 defm WriteALU  : X86SchedWritePair; // Simple integer ALU op.
-def WriteALURMW : WriteSequence<[WriteALULd, WriteRMW]>;
+def WriteALURMW : WriteSequence<[WriteALULd, WriteStore]>;
 defm WriteIMul : X86SchedWritePair; // Integer multiplication.
 def  WriteIMulH : SchedWrite;       // Integer multiplication, high part.
 defm WriteIDiv : X86SchedWritePair; // Integer division.
 def  WriteLEA  : SchedWrite;        // LEA instructions can't fold loads.
 
 defm WriteBitScan : X86SchedWritePair; // Bit scan forward/reverse.
 defm WritePOPCNT : X86SchedWritePair; // Bit population count.
 defm WriteLZCNT : X86SchedWritePair; // Leading zero count.
 defm WriteTZCNT : X86SchedWritePair; // Trailing zero count.
+defm WriteCMOV : X86SchedWritePair; // Conditional move.
+def  WriteSETCC : SchedWrite; // Set register based on condition code.
+def  WriteSETCCStore : WriteSequence<[WriteSETCC, WriteStore]>;
 
 // Integer shifts and rotates.
 defm WriteShift : X86SchedWritePair;
 
 // BMI1 BEXTR, BMI2 BZHI
 defm WriteBEXTR : X86SchedWritePair;
 defm WriteBZHI  : X86SchedWritePair;
 
-// Loads, stores, and moves, not folded with other operations.
-def WriteLoad  : SchedWrite;
-def WriteStore : SchedWrite;
-def WriteMove  : SchedWrite;
-
 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 // These can often bypass execution ports completely.
 def WriteZero : SchedWrite;
 
 // Branches don't produce values, so they have no latency, but they still
 // consume resources. Indirect branches can fold loads.
 defm WriteJump : X86SchedWritePair;
 

lib/Target/X86/X86ScheduleBtVer2.td

 // Arithmetic.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : JWriteResIntPair<WriteALU,   [JALU01], 1>;
 defm : JWriteResIntPair<WriteIMul,  [JALU1, JMul], 3, [1, 1], 2>; // i8/i16/i32 multiplication
 defm : JWriteResIntPair<WriteIDiv,  [JALU1, JDiv], 41, [1, 41], 2>; // Worst case (i64 division)
 defm : JWriteResIntPair<WriteCRC32, [JALU01], 3, [4], 3>;
 
+defm : JWriteResIntPair<WriteCMOV,  [JALU01], 1>; // Conditional move.
+def  : WriteRes<WriteSETCC, [JALU01]>; // Setcc.
+
 def  : WriteRes<WriteIMulH, [JALU1]> {
   let Latency = 6;
   let ResourceCycles = [4];
 }
 
 // This is for simple LEAs with one or two input operands.
 // FIXME: SAGU 3-operand LEA
 def : WriteRes<WriteLEA, [JALU01]>;

lib/Target/X86/X86ScheduleSLM.td

 def : InstRW<[WriteMove], (instrs COPY)>;
 
 defm : SLMWriteResPair<WriteALU,   [SLM_IEC_RSV01], 1>;
 defm : SLMWriteResPair<WriteIMul,  [SLM_IEC_RSV1],  3>;
 defm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0],  1>;
 defm : SLMWriteResPair<WriteJump,  [SLM_IEC_RSV1],  1>;
 defm : SLMWriteResPair<WriteCRC32, [SLM_IEC_RSV1],  3>;
 
+defm : SLMWriteResPair<WriteCMOV,  [SLM_IEC_RSV01], 1>;
+def  : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
+
 // This is for simple LEAs with one or two input operands.
 // The complex ones can only execute on port 1, and they require two cycles on
 // the port to read all inputs. We don't model that.
 def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
 
 // Bit counts.
 defm : SLMWriteResPair<WriteBitScan, [SLM_IEC_RSV01], 10, [20], 10>;
 defm : SLMWriteResPair<WriteLZCNT,   [SLM_IEC_RSV0], 3>;

lib/Target/X86/X86ScheduleZnver1.td

 def : WriteRes<WriteZero,  []>;
 def : WriteRes<WriteLEA, [ZnALU]>;
 defm : ZnWriteResPair<WriteALU,   [ZnALU], 1>;
 defm : ZnWriteResPair<WriteIMul,   [ZnALU1, ZnMultiplier], 4>;
 defm : ZnWriteResPair<WriteShift, [ZnALU], 1>;
 defm : ZnWriteResPair<WriteJump,  [ZnALU], 1>;
 defm : ZnWriteResFpuPair<WriteCRC32, [ZnFPU0], 3>;
 
+defm : ZnWriteResPair<WriteCMOV,   [ZnALU], 1>;
+def  : WriteRes<WriteSETCC,  [ZnALU]>;
+
 // Bit counts.
 defm : ZnWriteResPair<WriteBitScan, [ZnALU], 3>;
 defm : ZnWriteResPair<WriteLZCNT,   [ZnALU], 2>;
 defm : ZnWriteResPair<WriteTZCNT,   [ZnALU], 2>;
 defm : ZnWriteResPair<WritePOPCNT,  [ZnALU], 1>;
 
 // Treat misc copies as a move.
 def : InstRW<[WriteMove], (instrs COPY)>;

 // MOV.
 // r16,m.
 def : InstRW<[WriteALULd, ReadAfterLd], (instregex "MOV16rm")>;
 
 // MOVSX, MOVZX.
 // r,m.
 def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;
 
-// CMOVcc.
-// r,r.
-def : InstRW<[WriteALU],
-      (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rr")>;
-// r,m.
-def : InstRW<[WriteALULd, ReadAfterLd],
-      (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rm")>;
-
 // XCHG.
 // r,r.
 def ZnWriteXCHG : SchedWriteRes<[ZnALU]> {
   let NumMicroOps = 2;
   let ResourceCycles = [2];
 }
 
 def : InstRW<[ZnWriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>;

 // m,r,cl.
 def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)mrCL")>;
 
 // SETcc.
 // r.
 def : InstRW<[WriteShift],
              (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)r")>;
 // m.
 def : InstRW<[WriteShift],
              (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)m")>;
 
 //-- Misc instructions --//
 // CMPXCHG.
 def ZnWriteCMPXCHG : SchedWriteRes<[ZnAGU, ZnALU]> {
   let Latency = 8;
   let NumMicroOps = 5;
 }

test/CodeGen/X86/pr31045.ll

 
 ; Function Attrs: norecurse nounwind uwtable
 define void @_Z1av() local_unnamed_addr #0 {
 ; CHECK-LABEL: _Z1av:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl struct_obj_3+{{.*}}(%rip), %eax
 ; CHECK-NEXT:    movsbl {{.*}}(%rip), %ecx
 ; CHECK-NEXT:    movzbl {{.*}}(%rip), %edx
+; CHECK-NEXT:    movzbl {{.*}}(%rip), %esi
 ; CHECK-NEXT:    andl $1, %eax
-; CHECK-NEXT:    leal (%rax,%rax), %esi
-; CHECK-NEXT:    subl %ecx, %esi
-; CHECK-NEXT:    subl %edx, %esi
+; CHECK-NEXT:    leal (%rax,%rax), %edi
+; CHECK-NEXT:    subl %ecx, %edi
+; CHECK-NEXT:    subl %edx, %edi
 ; CHECK-NEXT:    xorl %ecx, %ecx
 ; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    cmovel %eax, %ecx
-; CHECK-NEXT:    movzbl {{.*}}(%rip), %edx
 ; CHECK-NEXT:    andl struct_obj_8+{{.*}}(%rip), %ecx
 ; CHECK-NEXT:    andl $1, %ecx
 ; CHECK-NEXT:    negl %ecx
-; CHECK-NEXT:    andl %edx, %ecx
+; CHECK-NEXT:    andl %esi, %ecx
 ; CHECK-NEXT:    negl %ecx
 ; CHECK-NEXT:    andl %eax, %ecx
 ; CHECK-NEXT:    negl %ecx
-; CHECK-NEXT:    testl %ecx, %esi
-; CHECK-NEXT:    notl %esi
-; CHECK-NEXT:    movzbl %sil, %eax
+; CHECK-NEXT:    testl %ecx, %edi
+; CHECK-NEXT:    notl %edi
+; CHECK-NEXT:    movzbl %dil, %eax
 ; CHECK-NEXT:    movw %ax, struct_obj_12+{{.*}}(%rip)
 ; CHECK-NEXT:    setne {{.*}}(%rip)
 ; CHECK-NEXT:    retq
 entry:
   %bf.load = load i32, i32* bitcast (i24* getelementptr inbounds (%struct.d.3.7.11.15.39.71.75.91.95.99.107.123.363, %struct.d.3.7.11.15.39.71.75.91.95.99.107.123.363* @struct_obj_3, i64 0, i32 0, i32 2) to i32*), align 2
   %tmp = load i8, i8* @var_46, align 1
   %conv1 = sext i8 %tmp to i32
   %tmp1 = load i8, i8* @var_49, align 1

test/CodeGen/X86/schedule-x86_64.ll

 ; SLM-NEXT:    sets %dil # sched: [1:0.50]
 ; SLM-NEXT:    setns %dil # sched: [1:0.50]
 ; SLM-NEXT:    setp %dil # sched: [1:0.50]
 ; SLM-NEXT:    setnp %dil # sched: [1:0.50]
 ; SLM-NEXT:    setl %dil # sched: [1:0.50]
 ; SLM-NEXT:    setge %dil # sched: [1:0.50]
 ; SLM-NEXT:    setle %dil # sched: [1:0.50]
 ; SLM-NEXT:    setg %dil # sched: [1:0.50]
-; SLM-NEXT:    seto (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    setno (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    setb (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    setae (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    sete (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    setne (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    setbe (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    seta (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    sets (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    setns (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    setp (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    setnp (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    setl (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    setge (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    setle (%rsi) # sched: [1:1.00]
-; SLM-NEXT:    setg (%rsi) # sched: [1:1.00]
+; SLM-NEXT:    seto (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    setno (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    setb (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    setae (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    sete (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    setne (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    setbe (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    seta (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    sets (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    setns (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    setp (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    setnp (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    setl (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    setge (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    setle (%rsi) # sched: [2:1.00]
+; SLM-NEXT:    setg (%rsi) # sched: [2:1.00]
 ; SLM-NEXT:    #NO_APP
 ; SLM-NEXT:    retq # sched: [4:1.00]
 ;
 ; SANDY-LABEL: test_setcc:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    seto %dil # sched: [1:0.50]
 ; SANDY-NEXT:    setno %dil # sched: [1:0.50]

 ; BTVER2-NEXT:    sets %dil # sched: [1:0.50]
 ; BTVER2-NEXT:    setns %dil # sched: [1:0.50]
 ; BTVER2-NEXT:    setp %dil # sched: [1:0.50]
 ; BTVER2-NEXT:    setnp %dil # sched: [1:0.50]
 ; BTVER2-NEXT:    setl %dil # sched: [1:0.50]
 ; BTVER2-NEXT:    setge %dil # sched: [1:0.50]
 ; BTVER2-NEXT:    setle %dil # sched: [1:0.50]
 ; BTVER2-NEXT:    setg %dil # sched: [1:0.50]
-; BTVER2-NEXT:    seto (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    setno (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    setb (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    setae (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    sete (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    setne (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    setbe (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    seta (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    sets (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    setns (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    setp (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    setnp (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    setl (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    setge (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    setle (%rsi) # sched: [1:1.00]
-; BTVER2-NEXT:    setg (%rsi) # sched: [1:1.00]
+; BTVER2-NEXT:    seto (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    setno (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    setb (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    setae (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    sete (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    setne (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    setbe (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    seta (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    sets (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    setns (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    setp (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    setnp (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    setl (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    setge (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    setle (%rsi) # sched: [2:1.00]
+; BTVER2-NEXT:    setg (%rsi) # sched: [2:1.00]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_setcc:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    seto %dil # sched: [1:0.25]
 ; ZNVER1-NEXT:    setno %dil # sched: [1:0.25]