Three new instructions:
umonitor - Sets up a linear address range to be
monitored by hardware and activates the monitor.
The address range should be a writeback memory
caching type.
umwait - A hint that allows the processor to
stop instruction execution and enter an
implementation-dependent optimized state
until occurrence of a class of events.
tpause - Directs the processor to enter an
implementation-dependent optimized state
until the TSC reaches the value in EDX:EAX.
Also modifying the description of the mfence
instruction, as the rep prefix (0xF3) was allowed
before, which would conflict with umonitor during
disassembly.
Before this patch
$ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble
.text mfence
After this patch
$ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble
.text umonitor %rax
What is the llvm-mc assembler expectation here? As this is defined it means that 64-bit mode assembly must alway use a 64-bit register and 32-bit mode must always use a 32-bit register. The documentation itself mentions being able to use a 16-bit register and that the 0x67 prefix has an effect, but that's not captured here.