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[X86] Add WriteBitScan/WriteLZCNT/WriteTZCNT/WritePOPCNT scheduler classes (PR36881)
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Authored by RKSimon on Mar 25 2018, 10:18 AM.

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Summary

Give the bit count instructions their own scheduler classes instead of forcing them into existing classes.

These were mostly overriden anyway, but I had to add in costs from Agner for silvermont and znver1 and the Fam16h SoG for btver2 (Jaguar)

Diff Detail

Repository
rL LLVM

Event Timeline

RKSimon created this revision.Mar 25 2018, 10:18 AM
GGanesh added inline comments.Mar 25 2018, 7:57 PM
lib/Target/X86/X86ScheduleBtVer2.td
141 ↗(On Diff #139742)

Looks good to me

lib/Target/X86/X86ScheduleZnver1.td
530 ↗(On Diff #139742)

Looks good to me!

craig.topper added inline comments.Mar 25 2018, 8:03 PM
lib/Target/X86/X86SchedSandyBridge.td
117 ↗(On Diff #139742)

Why are these not load latency 5? Aside from SNB not having these instructions?

RKSimon added inline comments.Mar 26 2018, 2:01 AM
lib/Target/X86/X86SchedSandyBridge.td
117 ↗(On Diff #139742)

Laziness ;-) As they didn't break any tests I put in the bare minimum - but I can add the extra info, although it will affect generic schedule values,

RKSimon updated this revision to Diff 139807.Mar 26 2018, 9:36 AM

Fixed load latencies for SB entries for use on the generic model

This revision is now accepted and ready to land.Mar 26 2018, 9:48 AM
This revision was automatically updated to reflect the committed changes.