[ARM] Change std::sort to llvm::sort in response to r327219

[mgrang]

Summary

r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

[mgrang]

Ping for reviews please.

[bkramer]

this is trivially fine.

llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
   MachineOperand STBase(MI->getOperand(2));
   STM.add(STBase).add(predOps(ARMCC::AL));
 
   // Sort the scratch registers into ascending order.
   const TargetRegisterInfo &TRI = getRegisterInfo();
   SmallVector<unsigned, 6> ScratchRegs;
   for(unsigned I = 5; I < MI->getNumOperands(); ++I)
     ScratchRegs.push_back(MI->getOperand(I).getReg());
-  std::sort(ScratchRegs.begin(), ScratchRegs.end(),
+  llvm::sort(ScratchRegs.begin(), ScratchRegs.end(),
              [&TRI](const unsigned &Reg1,
                     const unsigned &Reg2) -> bool {
                return TRI.getEncodingValue(Reg1) <
                       TRI.getEncodingValue(Reg2);
              });
 
   for (const auto &Reg : ScratchRegs) {
     LDM.addReg(Reg, RegState::Define);
     STM.addReg(Reg, RegState::Kill);
   }
 
   BB->erase(MI);
 }

llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp

for (; i != 0; --i) {
       // Omitting the kill flags is conservatively correct even if the live-in
       // is not used after all.
       Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn));
     }
 
     if (Regs.empty())
       continue;
 
-    std::sort(Regs.begin(), Regs.end(), [&](const RegAndKill &LHS,
+    llvm::sort(Regs.begin(), Regs.end(), [&](const RegAndKill &LHS,
                                              const RegAndKill &RHS) {
       return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first);
     });
 
     if (Regs.size() > 1 || StrOpc== 0) {
       MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
                                     .addReg(ARM::SP)
                                     .setMIFlags(MIFlags)
                                     .add(predOps(ARMCC::AL));
for (; i != 0; --i) {
 
       LastReg = Reg;
       Regs.push_back(Reg);
     }
 
     if (Regs.empty())
       continue;
 
-    std::sort(Regs.begin(), Regs.end(), [&](unsigned LHS, unsigned RHS) {
+    llvm::sort(Regs.begin(), Regs.end(), [&](unsigned LHS, unsigned RHS) {
       return TRI.getEncodingValue(LHS) < TRI.getEncodingValue(RHS);
     });
 
     if (Regs.size() > 1 || LdrOpc == 0) {
       MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
                                     .addReg(ARM::SP)
                                     .add(predOps(ARMCC::AL));
       for (unsigned i = 0, e = Regs.size(); i < e; ++i)

llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
   if (MemOps.size() > 0)
     FormCandidates(MemOps);
 
   // Sort candidates so they get processed from end to begin of the basic
   // block later; This is necessary for liveness calculation.
   auto LessThan = [](const MergeCandidate* M0, const MergeCandidate *M1) {
     return M0->InsertPos < M1->InsertPos;
   };
-  std::sort(Candidates.begin(), Candidates.end(), LessThan);
+  llvm::sort(Candidates.begin(), Candidates.end(), LessThan);
 
   // Go through list of candidates and merge.
   bool Changed = false;
   for (const MergeCandidate *Candidate : Candidates) {
     if (Candidate->CanMergeToLSMulti || Candidate->CanMergeToLSDouble) {
       MachineInstr *Merged = MergeOpsUpdate(*Candidate);
       // Merge preceding/trailing base inc/dec into the merged op.
       if (Merged) {

 
 bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
                                  SmallVectorImpl<MachineInstr *> &Ops,
                                  unsigned Base, bool isLd,
                                  DenseMap<MachineInstr*, unsigned> &MI2LocMap) {
   bool RetVal = false;
 
   // Sort by offset (in reverse order).
-  std::sort(Ops.begin(), Ops.end(),
+  llvm::sort(Ops.begin(), Ops.end(),
              [](const MachineInstr *LHS, const MachineInstr *RHS) {
                int LOffset = getMemoryOpOffset(*LHS);
                int ROffset = getMemoryOpOffset(*RHS);
                assert(LHS == RHS || LOffset != ROffset);
                return LOffset > ROffset;
              });
 
   // The loads / stores of the same base are in order. Scan them from first to
   // last and check for the following:
   // 1. Any def of base.
   // 2. Any gaps.
   while (Ops.size() > 1) {
     unsigned FirstLoc = ~0U;
     unsigned LastLoc = 0;

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp

if (FPU != ARM::FK_INVALID)
     emitFPUDefaultAttributes();
 
   if (Arch != ARM::ArchKind::INVALID)
     emitArchDefaultAttributes();
 
   if (Contents.empty())
     return;
 
-  std::sort(Contents.begin(), Contents.end(), AttributeItem::LessTag);
+  llvm::sort(Contents.begin(), Contents.end(), AttributeItem::LessTag);
 
   ARMELFStreamer &Streamer = getStreamer();
 
   // Switch to .ARM.attributes section
   if (AttributeSection) {
     Streamer.SwitchSection(AttributeSection);
   } else {
     AttributeSection = Streamer.getContext().getELFSection(