[X86][Znver1] Remove InstRWs for BLENDVPS/PD

[craig.topper]

Summary

This removes the InstRWs for BLENDVPS/PD in favor of WriteFVarBlend. The latency listed was 3 cycles but WriteFVarBlend is defined as 1 cycle latency. The 1 cycle latency matches Agner Fog's data.

The patterns were missing the VEX forms which is why there are no test changes. We don't test "-mcpu=znver1 -mattr=-avx"

[RKSimon]

The patterns were missing the VEX forms which is why there are no test changes. We don't test "-mcpu=znver1 -mattr=-avx"

Thanks for reminding me - we need to fix the sse schedule tests to not use the vex instructions. I'll look at replacing then with inline asm.

[craig.topper]

Why can't just explicitly set the sse level?

[RKSimon]

In D44841#1047129, @craig.topper wrote:

Why can't just explicitly set the sse level?

Yes, I can - it does mean that we'll lose VEX coverage for a lot of instructions - we can either add 2 entries for each target or I add tests to avx/avx2-schedule.

There are a few cost diffs (e.g. sandybridge cvtss2sirm is different to vcvtss2sirm).

[RKSimon]

In D44841#1047185, @RKSimon wrote:

In D44841#1047129, @craig.topper wrote:

Why can't just explicitly set the sse level?

Yes, I can - it does mean that we'll lose VEX coverage for a lot of instructions - we can either add 2 entries for each target or I add tests to avx/avx2-schedule.

There are a few cost diffs (e.g. sandybridge cvtss2sirm is different to vcvtss2sirm).

I've added these at rL328420/rL328421/rL328423

[craig.topper]

Rebase

[RKSimon]

@GGanesh Is there any reason why the SSE/AVX versions would differ? It doesn't look like pblendvb/vpblendvb has an equivalent diff.

[GGanesh]

It shouldn't differ.
The xmm version has 1 cycle latency and ymm version has 2 cycle latency for both AVX and SSE.

[RKSimon]

In D44841#1060902, @GGanesh wrote:

It shouldn't differ.
The xmm version has 1 cycle latency and ymm version has 2 cycle latency for both AVX and SSE.

OK - patch LGTM

lib/Target/X86/X86ScheduleZnver1.td

 // r32 <- x,y.
 def ZnWriteMOVMSKPr : SchedWriteRes<[ZnFPU2]> ;
 def : InstRW<[ZnWriteMOVMSKPr], (instregex "(V?)MOVMSKP(S|D)(Y?)rr")>;
 
 // VPERM2F128.
 def : InstRW<[WriteMicrocoded], (instregex "VPERM2F128rr")>;
 def : InstRW<[WriteMicrocoded], (instregex "VPERM2F128rm")>;
 
-// BLENDVP S/D.
-def ZnWriteFPU01Lat3 : SchedWriteRes<[ZnFPU013]> {
-  let Latency = 3;
-}
-def ZnWriteFPU01Lat3Ld : SchedWriteRes<[ZnAGU, ZnFPU013]> {
-  let Latency = 11;
-  let NumMicroOps = 2;
-  let ResourceCycles = [1, 2];
-}
-def : InstRW<[ZnWriteFPU01Lat3], (instregex "BLENDVP(S|D)rr0")>;
-def : InstRW<[ZnWriteFPU01Lat3Ld, ReadAfterLd], (instregex "BLENDVP(S|D)rm0")>;
-
 def ZnWriteBROADCAST : SchedWriteRes<[ZnAGU, ZnFPU13]> {
   let NumMicroOps = 2;
   let Latency = 8;
 }
 // VBROADCASTF128.
 def : InstRW<[ZnWriteBROADCAST], (instregex "VBROADCASTF128")>;
 
 // EXTRACTPS.