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[llvm-mca] Refactor class RegisterFile to allow the definition of multiple register files.
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Authored by andreadb on Mar 14 2018, 12:14 PM.

Details

Summary

This is a refactoring in preparation for other two changes that will allow scheduling models to define multiple register files. This is the first step towards fixing PR36662.

class RegisterFile (in Dispatch.h) now can be used to emulate multiple register files.
Internally, it tracks the number of temporary registers dynamically allocated by each register file (described by class RegisterFileInfo).
A RegisterFileInfo stores the number of temporary registers available, and the maximum number of temporary registers used at runtime. There is a RegisterFileInfo for every register file defined by the processor scheduling model. In the absence of register file definitions, a "default" RegisterFileInfo is created; the default RegisterFileInfo describes a register file with an unlimited number of temporaries.

Each register file is associated with a list of MCRegisterClass indices. Knowinb the register class indices allows to map physical registers to register files.

The long term goal is to allow processor models to optionally specify how many register files are implemented using the following tablegen syntax:

`def FPRegFile : RegisterFile<[RegisterClassA, RegisterClassB, ...], #NumTemps>`

Where: [RegisterClassA, RegisterClassB,...] is a list of RegisterClass records, and #NumTemps is the number of temporaries implemented by the register file.

This patch is a "NFCI" change that restructures the code in preparation for the future development to fix PR36662.
Once this patch is accepted, the plan is to send two other patches:

  1. A patch that adds the new tablegen syntax for defining RegisterFiles
  2. An llvm-mca patch that allows to query the model to obtain the register file descriptors.

Please let me know what you think.

Thanks,
Andrea

Diff Detail

Event Timeline

andreadb created this revision.Mar 14 2018, 12:14 PM

You can probably commit the Instruction/InstrDesc argument changes straightaway and simplify this patch

<pedantic> I think physical registers is a better term than temporary registers, I don't know what other people think?

Jaguar treats 1 ymm logical as (upto) 2 x 128-bit physical entries - real world perf effect is minimal, but it does mean that it performs (upto) 2 read/writes into the PRF. 128-bit physicals that are known zero don't take up an PRF entry and the read/write should be quicker.

<pedantic> I think physical registers is a better term than temporary registers, I don't know what other people think?

I agree in principle, but unfortunately LLVM already uses MCPhysReg to denote RAX/RBX/... so there is a risk of confusion. Agner sometimes uses "microarchitectural registers", which is a nice name, albeit a bit long. We could abbreviate to UarchReg ?

Jaguar treats 1 ymm logical as (upto) 2 x 128-bit physical entries - real world perf effect is minimal, but it does mean that it performs (upto) 2 read/writes into the PRF. 128-bit physicals that are known zero don't take up an PRF entry and the read/write should be quicker.

tools/llvm-mca/Dispatch.cpp
41

why not use a range ?

tools/llvm-mca/Dispatch.h
37

typo: "tracks"

39

XXXInfo ususally represents immutable information about XXX. What about calling this RegisterMappingTracker or something along those lines ?

43

const ?

72

typo: specific

108

Please document these.

Thanks for the feedback.

I am going to upload an updated patch soon.

<pedantic> I think physical registers is a better term than temporary registers, I don't know what other people think?

I agree in principle, but unfortunately LLVM already uses MCPhysReg to denote RAX/RBX/... so there is a risk of confusion. Agner sometimes uses "microarchitectural registers", which is a nice name, albeit a bit long. We could abbreviate to UarchReg ?

I like "microarchitectural register". I will use it for now.

tools/llvm-mca/Dispatch.h
39

I will use RegisterMappingTracker.

43

It can be changed by 'RegisterFile::isAvailable'.

Users can override the register file size using flag -register-file-size. If the number of "microarchitectural registers" is too small, there is a risk of deadlock in the dispatch logic. Method 'isAvailable' spots if there is a problems with the total number of mappings, and artificially increases to avoid problems. When the total number of mappings is created, a warning is generated to standard error to notify the user.

If you want, I can remove that check, and make this field const. We still want to identify potential deadlocks and abort with a fatal_error. What do you think?

108

Will do.

Jaguar treats 1 ymm logical as (upto) 2 x 128-bit physical entries - real world perf effect is minimal, but it does mean that it performs (upto) 2 read/writes into the PRF. 128-bit physicals that are known zero don't take up an PRF entry and the read/write should be quicker.

Right. Ideally we should be able to emulate that. That can be a future work.

andreadb updated this revision to Diff 138583.Mar 15 2018, 10:25 AM

Patch updated.
Please let me know what you think.

Cheers
-Andrea

A few minor comments but otherwise looks almost ready.

tools/llvm-mca/Dispatch.cpp
154

Better to do this in the constructor?

tools/llvm-mca/Dispatch.h
31–32

and and

78

Assert that there 32 or less PRFs?

80

for each

84

Please can you make it clear in the comment this WIP?

91

VR256RegClass

138

(style) Asserts should have a message as well as a condition.

courbet added inline comments.Mar 16 2018, 7:48 AM
tools/llvm-mca/Dispatch.cpp
153

remove "(0U)" ?

tools/llvm-mca/Dispatch.h
43

I see. Dying sounds reasonable. It does not really make sense for a microarchitecture to not even have enough microarchitectural registers to handle the registers its ISA defines. The user should know (or be told :) ) that.

andreadb updated this revision to Diff 138739.Mar 16 2018, 11:24 AM

Patch updated.
Address review comments.

andreadb updated this revision to Diff 138778.Mar 16 2018, 3:02 PM

Patch updated.
Forgot to add a string message to the new asserts.

andreadb marked 15 inline comments as done.Mar 16 2018, 3:03 PM
RKSimon accepted this revision.Mar 18 2018, 7:00 AM

LGTM with a couple of minors

tools/llvm-mca/Dispatch.cpp
30

Assert that RegisterFileIndex < 32 ? There may be other cases but this is the only one that I can find.

tools/llvm-mca/Dispatch.h
42

unbounded

This revision is now accepted and ready to land.Mar 18 2018, 7:00 AM
This revision was automatically updated to reflect the committed changes.