[ARM][Asm] VMOVSRR and VMOVRRS need sequential S registers

[olista01]

Summary

These instructions require that the two S registers are adjacent (but not the R registers), because only the first register is included in the encoding, but we were not checking this in the assembler.

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
                                                "predicable, but condition "
                                                "code specified");
     if (Imm8 == 0x14 && Pred != ARMCC::AL)
       return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
                                                "predicable, but condition "
                                                "code specified");
     break;
   }
+  case ARM::VMOVRRS: {
+    // Source registers must be sequential.
+    const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg());
+    const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg());
+    if (Sm1 != Sm + 1)
+      return Error(Operands[5]->getStartLoc(),
+                   "source operands must be sequential");
+    break;
+  }
+  case ARM::VMOVSRR: {
+    // Destination registers must be sequential.
+    const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg());
+    const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
+    if (Sm1 != Sm + 1)
+      return Error(Operands[3]->getStartLoc(),
+                   "destination operands must be sequential");
+    break;
+  }
   }
 
   return false;
 }
 
 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
   switch(Opc) {
   default: llvm_unreachable("unexpected opcode!");

llvm/trunk/test/MC/ARM/vmov-pair-diags.s

+@ RUN: not llvm-mc -triple armv7-eabi < %s 2>&1 | FileCheck %s
+
+vmov  r0, r1, s0, s2
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: source operands must be sequential
+vmov  s0, s2, r0, r1
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: destination operands must be sequential