[GlobalIsel][X86] Support G_INTTOPTR instruction.

[aivchenk]

Summary

Add legalization/selection for x86/x86_64 and
corresponding tests.

[igorb]

Could you please add test for Legalizar pass?

[aivchenk]

Added tests for legalizer

[aivchenk]

added legalizer tests

[igorb]

LGTM,
Thanks.

lib/Target/X86/X86InstructionSelector.cpp

case TargetOpcode::G_GLOBAL_VALUE:
     return selectGlobalValue(I, MRI, MF);
   case TargetOpcode::G_CONSTANT:
     return selectConstant(I, MRI, MF);
   case TargetOpcode::G_FCONSTANT:
     return materializeFP(I, MRI, MF);
   case TargetOpcode::G_PTRTOINT:
   case TargetOpcode::G_TRUNC:
     return selectTruncOrPtrToInt(I, MRI, MF);
+  case TargetOpcode::G_INTTOPTR:
+    return selectCopy(I, MRI);
   case TargetOpcode::G_ZEXT:
     return selectZext(I, MRI, MF);
   case TargetOpcode::G_ANYEXT:
     return selectAnyext(I, MRI, MF);
   case TargetOpcode::G_ICMP:
     return selectCmp(I, MRI, MF);
   case TargetOpcode::G_UADDE:
     return selectUadde(I, MRI, MF);

lib/Target/X86/X86LegalizerInfo.cpp

void X86LegalizerInfo::setLegalizerInfo32bit() {
 
   // Pointer-handling
   setAction({G_FRAME_INDEX, p0}, Legal);
   setAction({G_GLOBAL_VALUE, p0}, Legal);
 
   setAction({G_GEP, p0}, Legal);
   setAction({G_GEP, 1, s32}, Legal);
 
-  if (!Subtarget.is64Bit())
+  if (!Subtarget.is64Bit()) {
     getActionDefinitionsBuilder(G_PTRTOINT)
         .legalForCartesianProduct({s1, s8, s16, s32}, {p0})
         .maxScalar(0, s32)
         .widenScalarToNextPow2(0, /*Min*/ 8);
+    getActionDefinitionsBuilder(G_INTTOPTR).legalFor({s32, p0});
+  }
 
   // Control-flow
   setAction({G_BRCOND, s1}, Legal);
 
   // Constants
   for (auto Ty : {s8, s16, s32, p0})
     setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
 
for (unsigned MemOp : {G_LOAD, G_STORE})
     setAction({MemOp, s64}, Legal);
 
   // Pointer-handling
   setAction({G_GEP, 1, s64}, Legal);
   getActionDefinitionsBuilder(G_PTRTOINT)
       .legalForCartesianProduct({s1, s8, s16, s32, s64}, {p0})
       .maxScalar(0, s64)
       .widenScalarToNextPow2(0, /*Min*/ 8);
+  getActionDefinitionsBuilder(G_INTTOPTR).legalFor({s64, p0});
 
   // Constants
   setAction({TargetOpcode::G_CONSTANT, s64}, Legal);
 
   // Extensions
   for (unsigned extOp : {G_ZEXT, G_SEXT, G_ANYEXT}) {
     setAction({extOp, s64}, Legal);
   }

test/CodeGen/X86/GlobalISel/x86-legalize-inttoptr.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=i686-linux-gnu -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+
+  define i32* @inttoptr_p0_s32(i32 %val) {
+  entry:
+    %0 = inttoptr i32 %val to i32*
+    ret i32* %0
+  }
+
+...
+---
+name:            inttoptr_p0_s32
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+frameInfo:
+  maxAlignment:    4
+fixedStack:
+  - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: inttoptr_p0_s32
+    ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[LOAD]](s32)
+    ; CHECK: $eax = COPY [[INTTOPTR]](p0)
+    ; CHECK: RET 0, implicit $eax
+    %1:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    %0:_(s32) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    %2:_(p0) = G_INTTOPTR %0(s32)
+    $eax = COPY %2(p0)
+    RET 0, implicit $eax
+
+...

test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+
+  define i32* @inttoptr_p0_s32(i32 %val) {
+  entry:
+    %0 = inttoptr i32 %val to i32*
+    ret i32* %0
+  }
+
+...
+---
+name:            inttoptr_p0_s32
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+frameInfo:
+  maxAlignment:    4
+fixedStack:
+  - { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: inttoptr_p0_s32
+    ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; CHECK: $eax = COPY [[MOV32rm]]
+    ; CHECK: RET 0, implicit $eax
+    %1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+    %0:gpr(s32) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+    %2:gpr(p0) = G_INTTOPTR %0(s32)
+    $eax = COPY %2(p0)
+    RET 0, implicit $eax
+
+...

test/CodeGen/X86/GlobalISel/x86_64-legalize-inttoptr.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+
+  define i64* @inttoptr_p0_s64(i64 %val) {
+  entry:
+    %0 = inttoptr i64 %val to i64*
+    ret i64* %0
+  }
+
+...
+---
+name:            inttoptr_p0_s64
+alignment:       4
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.1.entry:
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: inttoptr_p0_s64
+    ; CHECK: liveins: $rdi
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
+    ; CHECK: $rax = COPY [[INTTOPTR]](p0)
+    ; CHECK: RET 0, implicit $rax
+    %0:_(s64) = COPY $rdi
+    %1:_(p0) = G_INTTOPTR %0(s64)
+    $rax = COPY %1(p0)
+    RET 0, implicit $rax
+
+...

test/CodeGen/X86/GlobalISel/x86_64-select-inttoptr.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+
+  define i64* @inttoptr_p0_s64(i64 %val) {
+  entry:
+    %0 = inttoptr i64 %val to i64*
+    ret i64* %0
+  }
+
+...
+---
+name:            inttoptr_p0_s64
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+body:             |
+  bb.1.entry:
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: inttoptr_p0_s64
+    ; CHECK: liveins: $rdi
+    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+    ; CHECK: $rax = COPY [[COPY]]
+    ; CHECK: RET 0, implicit $rax
+    %0:gpr(s64) = COPY $rdi
+    %1:gpr(p0) = G_INTTOPTR %0(s64)
+    $rax = COPY %1(p0)
+    RET 0, implicit $rax
+
+...