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Commit c01f750

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author
Alexander Ivchenko
committedFeb 28, 2018
[GlobalIsel][X86] Support G_INTTOPTR instruction.
Add legalization/selection for x86/x86_64 and corresponding tests. Reviewed By: igorb Differential Revision: https://reviews.llvm.org/D43622 llvm-svn: 326320
1 parent 256869d commit c01f750

7 files changed

+167
-1
lines changed
 

‎llvm/lib/Target/X86/X86InstructionSelector.cpp

+2
Original file line numberDiff line numberDiff line change
@@ -350,6 +350,8 @@ bool X86InstructionSelector::select(MachineInstr &I,
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case TargetOpcode::G_PTRTOINT:
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case TargetOpcode::G_TRUNC:
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return selectTruncOrPtrToInt(I, MRI, MF);
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case TargetOpcode::G_INTTOPTR:
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return selectCopy(I, MRI);
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case TargetOpcode::G_ZEXT:
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return selectZext(I, MRI, MF);
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case TargetOpcode::G_ANYEXT:

‎llvm/lib/Target/X86/X86LegalizerInfo.cpp

+4-1
Original file line numberDiff line numberDiff line change
@@ -124,11 +124,13 @@ void X86LegalizerInfo::setLegalizerInfo32bit() {
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setAction({G_GEP, p0}, Legal);
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setAction({G_GEP, 1, s32}, Legal);
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127-
if (!Subtarget.is64Bit())
127+
if (!Subtarget.is64Bit()) {
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getActionDefinitionsBuilder(G_PTRTOINT)
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.legalForCartesianProduct({s1, s8, s16, s32}, {p0})
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.maxScalar(0, s32)
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.widenScalarToNextPow2(0, /*Min*/ 8);
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getActionDefinitionsBuilder(G_INTTOPTR).legalFor({s32, p0});
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}
132134

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// Control-flow
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setAction({G_BRCOND, s1}, Legal);
@@ -194,6 +196,7 @@ void X86LegalizerInfo::setLegalizerInfo64bit() {
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.legalForCartesianProduct({s1, s8, s16, s32, s64}, {p0})
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.maxScalar(0, s64)
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.widenScalarToNextPow2(0, /*Min*/ 8);
199+
getActionDefinitionsBuilder(G_INTTOPTR).legalFor({s64, p0});
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// Constants
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setAction({TargetOpcode::G_CONSTANT, s64}, Legal);
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=CHECK
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define i64* @inttoptr_p0_s64(i64 %val) {
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; CHECK-LABEL: inttoptr_p0_s64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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entry:
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%0 = inttoptr i64 %val to i64*
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ret i64* %0
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}
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=i686-linux-gnu -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define i32* @inttoptr_p0_s32(i32 %val) {
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entry:
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%0 = inttoptr i32 %val to i32*
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ret i32* %0
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}
11+
12+
...
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---
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name: inttoptr_p0_s32
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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frameInfo:
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maxAlignment: 4
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fixedStack:
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- { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true }
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body: |
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bb.1.entry:
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; CHECK-LABEL: name: inttoptr_p0_s32
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; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
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; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0)
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; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[LOAD]](s32)
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; CHECK: $eax = COPY [[INTTOPTR]](p0)
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; CHECK: RET 0, implicit $eax
33+
%1:_(p0) = G_FRAME_INDEX %fixed-stack.0
34+
%0:_(s32) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
35+
%2:_(p0) = G_INTTOPTR %0(s32)
36+
$eax = COPY %2(p0)
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RET 0, implicit $eax
38+
39+
...
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3+
4+
--- |
5+
6+
define i32* @inttoptr_p0_s32(i32 %val) {
7+
entry:
8+
%0 = inttoptr i32 %val to i32*
9+
ret i32* %0
10+
}
11+
12+
...
13+
---
14+
name: inttoptr_p0_s32
15+
alignment: 4
16+
legalized: true
17+
regBankSelected: true
18+
tracksRegLiveness: true
19+
registers:
20+
- { id: 0, class: gpr }
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- { id: 1, class: gpr }
22+
- { id: 2, class: gpr }
23+
frameInfo:
24+
maxAlignment: 4
25+
fixedStack:
26+
- { id: 0, size: 4, alignment: 16, stack-id: 0, isImmutable: true }
27+
body: |
28+
bb.1.entry:
29+
; CHECK-LABEL: name: inttoptr_p0_s32
30+
; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.0, align 0)
31+
; CHECK: $eax = COPY [[MOV32rm]]
32+
; CHECK: RET 0, implicit $eax
33+
%1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
34+
%0:gpr(s32) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
35+
%2:gpr(p0) = G_INTTOPTR %0(s32)
36+
$eax = COPY %2(p0)
37+
RET 0, implicit $eax
38+
39+
...
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,35 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
3+
4+
--- |
5+
6+
define i64* @inttoptr_p0_s64(i64 %val) {
7+
entry:
8+
%0 = inttoptr i64 %val to i64*
9+
ret i64* %0
10+
}
11+
12+
...
13+
---
14+
name: inttoptr_p0_s64
15+
alignment: 4
16+
tracksRegLiveness: true
17+
registers:
18+
- { id: 0, class: _ }
19+
- { id: 1, class: _ }
20+
body: |
21+
bb.1.entry:
22+
liveins: $rdi
23+
24+
; CHECK-LABEL: name: inttoptr_p0_s64
25+
; CHECK: liveins: $rdi
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
27+
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
28+
; CHECK: $rax = COPY [[INTTOPTR]](p0)
29+
; CHECK: RET 0, implicit $rax
30+
%0:_(s64) = COPY $rdi
31+
%1:_(p0) = G_INTTOPTR %0(s64)
32+
$rax = COPY %1(p0)
33+
RET 0, implicit $rax
34+
35+
...
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3+
4+
--- |
5+
6+
define i64* @inttoptr_p0_s64(i64 %val) {
7+
entry:
8+
%0 = inttoptr i64 %val to i64*
9+
ret i64* %0
10+
}
11+
12+
...
13+
---
14+
name: inttoptr_p0_s64
15+
alignment: 4
16+
legalized: true
17+
regBankSelected: true
18+
tracksRegLiveness: true
19+
registers:
20+
- { id: 0, class: gpr }
21+
- { id: 1, class: gpr }
22+
body: |
23+
bb.1.entry:
24+
liveins: $rdi
25+
26+
; CHECK-LABEL: name: inttoptr_p0_s64
27+
; CHECK: liveins: $rdi
28+
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
29+
; CHECK: $rax = COPY [[COPY]]
30+
; CHECK: RET 0, implicit $rax
31+
%0:gpr(s64) = COPY $rdi
32+
%1:gpr(p0) = G_INTTOPTR %0(s64)
33+
$rax = COPY %1(p0)
34+
RET 0, implicit $rax
35+
36+
...

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