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[mips][lld] Spectre variant two mitigation for MIPSR2

Authored by sdardis on Feb 19 2018, 2:52 PM.



This patch provides migitation for CVE-2017-5715, Spectre variant two,
which affects the P5600 and P6600. It implements the LLD part of
-z hazardplt. Like the Clang part of this patch, I have opted for that
specific option name in case alternative migitation methods are required
in the future.

The migitation strategy suggested by MIPS for these processors is to use
hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard
barrier variants of the 'jalr' and 'jr' instructions respectively.

These instructions impede the execution of instruction stream until
architecturally defined hazards (changes to the instruction stream,
privileged registers which may affect execution) are cleared. These
instructions in MIPS' designs are not speculated past.

These instructions are defined by the MIPS32R2 ISA, so this mitigation
method is not compatible with processors which implement an earlier
revision of the MIPS ISA.

For LLD, this changes PLT stubs to use 'jalr.hb' and 'jr.hb'.

Diff Detail

rLLD LLVM Linker

Event Timeline

sdardis created this revision.Feb 19 2018, 2:52 PM
This revision is now accepted and ready to land.Feb 20 2018, 12:20 AM
This revision was automatically updated to reflect the committed changes.
This revision was automatically updated to reflect the committed changes.
ruiu added a comment.Feb 21 2018, 11:20 AM



It's better to use uint32_t if it is intended to be unsigned 32-bit integer.

sdardis marked an inline comment as done.Feb 21 2018, 12:04 PM
sdardis added inline comments.

Thanks, rL325713.