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[X86] Add phony registers for high halves of E[A-D]X, E[SD]I, E[BS]P and EIP
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Authored by kparzysz on Feb 15 2018, 2:18 PM.

Details

Summary

The intent for this is to model the upper halves of EAX et al as individual entities (although not addressable). The motivation comes from the fact that modifying AX does not modify the upper half of EAX, whereas currently AX and EAX share the exact same set of register units. The same register units for both imply that writing AX overwrites EAX, which lead to issues in using RDF with the X86 backend.

Simply adding the extra registers without putting them in a register class causes compile-time assertions in TargetRegisterInfo::getMinimalPhysRegClass. With the extra registers in a register class, the pressure sets/limits change due to extra register classes synthesized by TableGen, and the resulting codegen is different from the original.

This patch introduces a concept of "artificial" registers, which take part in register aliasing analysis, but do not cause any changes to register pressure sets/limits, etc. No additional register classes are created due to the existence of these registers or the associated subregister indexes.

To summarize the concepts:

A register in the .td file can be designated as "artificial", which means that it doesn't correspond to any physical register in the associated architecture. This may be useful for creating registers that correspond to otherwise unaddressable parts of actual (non-artificial) registers.

Within TableGen there are several other entities that be artificial: subregister index, register unit and register class.

A subregister index is artificial if it cannot be used to obtain a non-artificial register from any other non-artificial register. In other words, if all registers obtained from applying this subregister index are artificial, then the index is considered artificial.

A register unit is considered artificial if any of the root registers is artificial. Specifically, units that are explicit aliases with an artificial register are also considered artificial.

A register class is artificial if all its members (registers) are artificial.

The main point of this is to avoid changing register pressure sets and weights due to an introduction of artificial registers: artificial register units are treated as having 0 weight, artificial subregister indices will not force new register classes from being created, artificial register classes will not have any register classes derived from them.

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kparzysz created this revision.Feb 15 2018, 2:18 PM
kparzysz added inline comments.
utils/TableGen/CodeGenRegisters.cpp
1163

Drat.

This should be a good thing! Among other things it should also allow us to switch register mask operands from physical registers to register units.

However we should double check the effect of this change on peak memory use and compilation time.

kparzysz updated this revision to Diff 135656.Feb 23 2018, 9:53 AM
kparzysz edited the summary of this revision. (Show Details)

This is a working patch with all necessary updates to affected testcases.

Also, updated the summary with more information.

However we should double check the effect of this change on peak memory use and compilation time.

Do you have any suggestions as to how the peak memory usage could be measured?

Time to compile LLVM+clang+projects, release+assertions using make -j1 (on x86-64):

Without the patch:

real    369m26.804s
user    358m58.346s
sys     10m26.244s

With the patch:

real    369m40.273s
user    358m57.061s
sys     10m40.756s

Hi Krzysztof,

Thanks for doing this.
In particular, that should help with our pressure estimation bug (https://bugs.llvm.org/show_bug.cgi?id=23423).

I haven't reviewed the patch in details, but I like the original direction.

Cheers,
-Quentin

Ping.

From what I understand about the pressure estimation bug, this approach could indeed help. For example BP could have two artificial subregisters: BPL and BPH, which would likely eliminate the synthetic units that affect the weights.

qcolombet accepted this revision.Mar 14 2018, 9:10 PM

Hi Krzysztof,

LGTM.

Could you add a small tablegen test case?

Thanks,
-Quentin

This revision is now accepted and ready to land.Mar 14 2018, 9:10 PM
This revision was automatically updated to reflect the committed changes.

Sorry for the archaelogy here.

Why don't we need artificial registers covering bits 31:16 of R8-R15? Or 15:8 of RBP/RSP/RSI/RDI/R8-R15?

We do. Fixed in r336134.

Here, a completely new and important concept is introduced into LLVM, and the patch description describes the new concept completely.

However, the relevant documentation is updated not at all.

The new field isn't even documented in the Target.td file.

The ONLY way to learn what isArtificial does, is to either read all these individual changes and understand their impacts, or to Google to find this particular change request.

Respectfully, this is no way to run a railroad. Please be nice to the programmers of the future.

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