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Differential D43291

[ARM] f16 vcmp fixes
ClosedPublic

Authored by SjoerdMeijer on Feb 14 2018, 7:33 AM.

Details

Reviewers
samparker
olista01
Commits
rG9430c8cd1c6f: [ARM] f16 vcmp fixes
rL325228: [ARM] f16 vcmp fixes
Summary

This adds a VCMPEZH match rule and fixes the f16 VCMP test cases.

Diff Detail

Event Timeline

SjoerdMeijer created this revision.Feb 14 2018, 7:33 AM
Herald added subscribers: kristof.beyls, javed.absar. · View Herald TranscriptFeb 14 2018, 7:33 AM
samparker added inline comments.Feb 14 2018, 8:05 AM
test/CodeGen/ARM/fp16-instructions.ll
126

Should this be testing CHECK-HARDFP-FULLFP16-NOT instead?

132

Do we need a VCMP_IMM test too? Or am I missing something?

olista01 added inline comments.Feb 14 2018, 8:52 AM
lib/Target/ARM/ARMInstrVFP.td
627

Could we also add the pattern for VCMPZH?

SjoerdMeijer updated this revision to Diff 134291.Feb 14 2018, 12:06 PM

Thanks for reviewing, comments addressed.

samparker accepted this revision.Feb 15 2018, 2:27 AM

LGTM, cheers.

This revision is now accepted and ready to land.Feb 15 2018, 2:27 AM
Closed by commit rL325228: [ARM] f16 vcmp fixes (authored by SjoerdMeijer). · Explain WhyFeb 15 2018, 2:36 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
ARM/
4 lines
test/
CodeGen/
ARM/
43 lines

Diff 134227

lib/Target/ARM/ARMInstrVFP.td

Show First 20 Lines • Show All 588 Lines • ▼ Show 20 Linesdef VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
let Inst{5} = 0; let Inst{5} = 0;
// Some single precision VFP instructions may be executed on both NEON and // Some single precision VFP instructions may be executed on both NEON and
// VFP pipelines on A8. // VFP pipelines on A8.
let D = VFPNeonA8Domain; let D = VFPNeonA8Domain;
} }
def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0, def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0,
(outs), (ins SPR:$Sd), (outs), (ins HPR:$Sd),
IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0", IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0",
[]> { [(arm_cmpfp0 HPR:$Sd, (i32 1))]> {
let Inst{3-0} = 0b0000; let Inst{3-0} = 0b0000;
let Inst{5} = 0; let Inst{5} = 0;
} }
def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
(outs), (ins DPR:$Dd), (outs), (ins DPR:$Dd),
IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
[(arm_cmpfp0 (f64 DPR:$Dd), (i32 0))]> { [(arm_cmpfp0 (f64 DPR:$Dd), (i32 0))]> {
Show All 11 Linesdef VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
// Some single precision VFP instructions may be executed on both NEON and // Some single precision VFP instructions may be executed on both NEON and
// VFP pipelines on A8. // VFP pipelines on A8.
let D = VFPNeonA8Domain; let D = VFPNeonA8Domain;
} }
def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0, def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0,
(outs), (ins SPR:$Sd), (outs), (ins SPR:$Sd),
IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0", IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0",
[]> { []> {
olista01Unsubmitted
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Could we also add the pattern for VCMPZH?

olista01: Could we also add the pattern for VCMPZH?
let Inst{3-0} = 0b0000; let Inst{3-0} = 0b0000;
let Inst{5} = 0; let Inst{5} = 0;
} }
} // Defs = [FPSCR_NZCV] } // Defs = [FPSCR_NZCV]
def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
(outs DPR:$Dd), (ins SPR:$Sm), (outs DPR:$Dd), (ins SPR:$Sm),
IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm", IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
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test/CodeGen/ARM/fp16-instructions.ll

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
define zeroext i1 @VCMP(float %F.coerce, float %G.coerce) { define zeroext i1 @VCMP(float %F.coerce, float %G.coerce) {
entry: entry:
%0 = bitcast float %F.coerce to i32 %0 = bitcast float %F.coerce to i32
%tmp.0.extract.trunc = trunc i32 %0 to i16 %tmp.0.extract.trunc = trunc i32 %0 to i16
%1 = bitcast i16 %tmp.0.extract.trunc to half %1 = bitcast i16 %tmp.0.extract.trunc to half
%2 = bitcast float %G.coerce to i32 %2 = bitcast float %G.coerce to i32
%tmp1.0.extract.trunc = trunc i32 %2 to i16 %tmp1.0.extract.trunc = trunc i32 %2 to i16
%3 = bitcast i16 %tmp1.0.extract.trunc to half %3 = bitcast i16 %tmp1.0.extract.trunc to half
%cmp = fcmp ogt half %1, %3 %cmp = fcmp une half %1, %3
ret i1 %cmp ret i1 %cmp
; CHECK-LABEL: VCMP: ; CHECK-LABEL: VCMP:
; CHECK-SOFT: bl __aeabi_fcmpgt ; CHECK-SOFT: bl __aeabi_fcmpeq
; CHECK-SOFTFP-VFP3: bl __aeabi_h2f ; CHECK-SOFTFP-VFP3: bl __aeabi_h2f
; CHECK-SOFTFP-VFP3: bl __aeabi_h2f ; CHECK-SOFTFP-VFP3: bl __aeabi_h2f
; CHECK-SOFTFP-VFP3: vcmpe.f32 s{{.}}, s{{.}} ; CHECK-SOFTFP-VFP3: vcmp.f32 s{{.}}, s{{.}}
; CHECK-SOFTFP-FP16: vcvtb.f32.f16 s{{.}}, s{{.}} ; CHECK-SOFTFP-FP16: vcvtb.f32.f16 s{{.}}, s{{.}}
; CHECK-SOFTFP-FP16: vcvtb.f32.f16 s{{.}}, s{{.}} ; CHECK-SOFTFP-FP16: vcvtb.f32.f16 s{{.}}, s{{.}}
; CHECK-SOFTFP-FP16: vcmpe.f32 s{{.}}, s{{.}} ; CHECK-SOFTFP-FP16: vcmp.f32 s{{.}}, s{{.}}
; CHECK-SOFTFP-FULLFP16: vmov.f16 [[S2:s[0-9]]], r0 ; CHECK-SOFTFP-FULLFP16: vmov.f16 [[S2:s[0-9]]], r0
; CHECK-SOFTFP-FULLFP16: vmov.f16 [[S0:s[0-9]]], r1 ; CHECK-SOFTFP-FULLFP16: vmov.f16 [[S0:s[0-9]]], r1
; CHECK-SOFTFP-FULLFP16: vcmpe.f16 [[S2]], [[S0]] ; CHECK-SOFTFP-FULLFP16: vcmp.f16 [[S2]], [[S0]]
; CHECK-SOFTFP-FULLFP16-NOT: vmov.f16 s{{.}}, r0 ; CHECK-SOFTFP-FULLFP16-NOT: vmov.f16 s{{.}}, r0
samparkerUnsubmitted
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Should this be testing CHECK-HARDFP-FULLFP16-NOT instead?

samparker: Should this be testing CHECK-HARDFP-FULLFP16-NOT instead?
; CHECK-SOFTFP-FULLFP16-NOT: vmov.f16 s{{.}}, r1 ; CHECK-SOFTFP-FULLFP16-NOT: vmov.f16 s{{.}}, r1
; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, s1 ; CHECK-HARDFP-FULLFP16: vcmp.f16 s0, s1
} }
; 4. VCMPE ; 4. VCMPE
define i32 @VCMPE_IMM(float %F.coerce) {
samparkerUnsubmitted
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Do we need a VCMP_IMM test too? Or am I missing something?

samparker: Do we need a VCMP_IMM test too? Or am I missing something?
entry:
%0 = bitcast float %F.coerce to i32
%tmp.0.extract.trunc = trunc i32 %0 to i16
%1 = bitcast i16 %tmp.0.extract.trunc to half
%tmp = fcmp olt half %1, 0.000000e+00
%tmp1 = zext i1 %tmp to i32
ret i32 %tmp1
; FIXME: enable when constant pool is fixed ; CHECK-LABEL: VCMPE_IMM:
;
;define i32 @VCMPE_IMM(float %F.coerce) { ; CHECK-SOFT: bl __aeabi_fcmplt
;entry: ; CHECK-SOFTFP-FP16: vcmpe.f32 s0, #0
; %0 = bitcast float %F.coerce to i32 ; CHECK-SOFTFP-FULLFP16: vcmpe.f16 s0, #0
; %tmp.0.extract.trunc = trunc i32 %0 to i16 ; CHECK-HARDFP-FULLFP16: vcmpe.f16 s0, #0
; %1 = bitcast i16 %tmp.0.extract.trunc to half }
; %tmp = fcmp olt half %1, 1.000000e+00
; %tmp1 = zext i1 %tmp to i32
; ret i32 %tmp1
;}
define i32 @VCMPE(float %F.coerce, float %G.coerce) { define i32 @VCMPE(float %F.coerce, float %G.coerce) {
entry: entry:
%0 = bitcast float %F.coerce to i32 %0 = bitcast float %F.coerce to i32
%tmp.0.extract.trunc = trunc i32 %0 to i16 %tmp.0.extract.trunc = trunc i32 %0 to i16
%1 = bitcast i16 %tmp.0.extract.trunc to half %1 = bitcast i16 %tmp.0.extract.trunc to half
%2 = bitcast float %G.coerce to i32 %2 = bitcast float %G.coerce to i32
%tmp.1.extract.trunc = trunc i32 %2 to i16 %tmp.1.extract.trunc = trunc i32 %2 to i16
%3 = bitcast i16 %tmp.1.extract.trunc to half %3 = bitcast i16 %tmp.1.extract.trunc to half
%tmp = fcmp olt half %1, %3 %tmp = fcmp olt half %1, %3
%tmp1 = zext i1 %tmp to i32 %tmp1 = zext i1 %tmp to i32
ret i32 %tmp1 ret i32 %tmp1
; CHECK-LABEL: VCMPE: ; CHECK-LABEL: VCMPE:
; CHECK-SOFT: bl __aeabi_fcmplt
; CHECK-SOFTFP-FP16: vcmpe.f32 s{{.}}, s{{.}}
; CHECK-SOFTFP-FULLFP16: vcmpe.f16 s{{.}}, s{{.}}
; CHECK-HARDFP-FULLFP16: vcmpe.f16 s{{.}}, s{{.}}
} }
; 5. VCVT (between floating-point and fixed-point) ; 5. VCVT (between floating-point and fixed-point)
; Only assembly/disassembly support ; Only assembly/disassembly support
; 6. VCVT (between floating-point and integer, both directions) ; 6. VCVT (between floating-point and integer, both directions)
define i32 @fptosi(i32 %A.coerce) { define i32 @fptosi(i32 %A.coerce) {
entry: entry:
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