[ARM] Fix disassembly of invalid banked register moves

[olista01]

Summary

When disassembling banked register move instructions, we don't have an
assembly syntax for the unallocated register numbers, so we have to
return Fail rather than SoftFail. Previously we were returning SoftFail,
then crashing in the InstPrinter as we have no way to represent these
encodings in an assembly string.

This also switches the decoder to use the table-generated list of banked
registers, removing the duplicated list of encodings.

[SjoerdMeijer]

Looks like a very sensible clean up and improvement to me.

Was only wondering about the Cortex-A8 -> A15 change in the test run line.

[olista01]

Was only wondering about the Cortex-A8 -> A15 change in the test run line.

That's because these banked register instructions were added with the virtualization extension.

llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
                                     uint64_t Address, const void *Decoder) {
   unsigned R = fieldFromInstruction(Val, 5, 1);
   unsigned SysM = fieldFromInstruction(Val, 0, 5);
 
   // The table of encodings for these banked registers comes from B9.2.3 of the
   // ARM ARM. There are patterns, but nothing regular enough to make this logic
   // neater. So by fiat, these values are UNPREDICTABLE:
-  if (!R) {
-    if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
-        SysM == 0x1a || SysM == 0x1b)
-      return MCDisassembler::SoftFail;
-  } else {
-    if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
-        SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
-      return MCDisassembler::SoftFail;
-  }
+  if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
+    return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createImm(Val));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
                                         uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;

llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt

-# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple armv7 2>&1 | FileCheck %s
+# RUN: not llvm-mc -disassemble %s -mcpu cortex-a15 -triple armv7 2>&1 | FileCheck %s
 
 # This file is checking ARMv7 encodings which are globally invalid, usually due
 # to the constraints of the instructions not being met. For example invalid
 # combinations of registers.
 
 
 #------------------------------------------------------------------------------
 # Undefined encodings for bfi

 # -------------------------------------------------------------------------------------------------
 # | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1|
 # -------------------------------------------------------------------------------------------------
 # 
 # 'a' == 1 and data_size == 8 is invalid
 [0x3d 0x3c 0xa0 0xf4]
 # CHECK: invalid instruction encoding
 # CHECK-NEXT: [0x3d 0x3c 0xa0 0xf4]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for MSR/MRS (banked register)
+#------------------------------------------------------------------------------
+# These have a banked register encoding of 0b111111, which is unallocated.
+
+# msr <invalid>, r0
+[0x00,0xf3,0x6f,0xe1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x00,0xf3,0x6f,0xe1]
+
+# mrs r0, <invalid>
+[0x00,0x03,0x4f,0xe1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x00,0x03,0x4f,0xe1]

llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt

-# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V7
+# RUN: not llvm-mc -disassemble %s -mcpu cortex-a15 -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V7
 # RUN: not llvm-mc -disassemble %s -mcpu cortex-a53 -triple thumbv8 2>&1 | FileCheck %s
 
 # This file is checking Thumbv7 encodings which are globally invalid, usually due
 # to the constraints of the instructions not being met. For example invalid
 # combinations of registers.
 
 #------------------------------------------------------------------------------
 # Undefined encoding for b.cc

 
 [0x00 0xf0 0x00 0x0d]
 # CHECK-V7: warning: potentially undefined instruction encoding
 # CHECK-V7-NEXT: [0x00 0xf0 0x00 0x0d]
 
 [0x63 0xeb 0x2d 0x46]
 # CHECK-V7: warning: potentially undefined instruction encoding
 # CHECK-V7-NEXT: [0x63 0xeb 0x2d 0x46]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for MSR/MRS (banked register)
+#------------------------------------------------------------------------------
+# These have a banked register encoding of 0b111111, which is unallocated.
+
+# msr <invalid>, r0
+[0x90,0xf3,0x30,0x8f]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x90,0xf3,0x30,0x8f]
+
+# mrs r0, <invalid>
+[0xff,0xf3,0x30,0x80]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xff,0xf3,0x30,0x80]