[AMDGPU] More descriptive names in the memory legalizer

[rampitec]

Summary

NFC.

[kzhuravl]

LGTM.

llvm/trunk/lib/Target/AMDGPU/SIMemoryLegalizer.cpp

public:
   static Optional<SIMemOpInfo> getStoreInfo(
       const MachineBasicBlock::iterator &MI);
   /// \returns Atomic fence info if \p MI is an atomic fence operation,
   /// "None" otherwise.
   static Optional<SIMemOpInfo> getAtomicFenceInfo(
       const MachineBasicBlock::iterator &MI);
   /// \returns Atomic cmpxchg/rmw info if \p MI is an atomic cmpxchg or
   /// rmw operation, "None" otherwise.
-  static Optional<SIMemOpInfo> getAtomicCmpxchgInfo(
+  static Optional<SIMemOpInfo> getAtomicCmpxchgOrRmwInfo(
       const MachineBasicBlock::iterator &MI);
 
   /// \brief Reports unknown synchronization scope used in \p MI to LLVM
   /// context.
   static void reportUnknownSyncScope(
       const MachineBasicBlock::iterator &MI);
 };
 
 class SIMemoryLegalizer final : public MachineFunctionPass {
 private:
   /// \brief Machine module info.
   const AMDGPUMachineModuleInfo *MMI = nullptr;
 
   /// \brief Instruction info.
   const SIInstrInfo *TII = nullptr;
 
   /// \brief Immediate for "vmcnt(0)".
   unsigned Vmcnt0Immediate = 0;
 
   /// \brief Opcode for cache invalidation instruction (L1).
-  unsigned Wbinvl1Opcode = 0;
+  unsigned VmemSIMDCacheInvalidateOpc = 0;
 
   /// \brief List of atomic pseudo instructions.
   std::list<MachineBasicBlock::iterator> AtomicPseudoMIs;
 
   /// \brief Sets named bit (BitName) to "true" if present in \p MI. Returns
   /// true if \p MI is modified, false otherwise.
   template <uint16_t BitName>
   bool enableNamedBit(const MachineBasicBlock::iterator &MI) const {
private:
   /// \brief Sets SLC bit to "true" if present in \p MI. Returns true if \p MI
   /// is modified, false otherwise.
   bool enableSLCBit(const MachineBasicBlock::iterator &MI) const {
     return enableNamedBit<AMDGPU::OpName::slc>(MI);
   }
 
   /// \brief Inserts "buffer_wbinvl1_vol" instruction \p Before or after \p MI.
   /// Always returns true.
-  bool insertBufferWbinvl1Vol(MachineBasicBlock::iterator &MI,
+  bool insertVmemSIMDCacheInvalidate(MachineBasicBlock::iterator &MI,
                                      bool Before = true) const;
   /// \brief Inserts "s_waitcnt vmcnt(0)" instruction \p Before or after \p MI.
   /// Always returns true.
   bool insertWaitcntVmcnt0(MachineBasicBlock::iterator &MI,
                            bool Before = true) const;
 
   /// \brief Removes all processed atomic pseudo instructions from the current
   /// function. Returns true if current function is modified, false otherwise.
   bool removeAtomicPseudoMIs();
 
   /// \brief Expands load operation \p MI. Returns true if instructions are
   /// added/deleted or \p MI is modified, false otherwise.
   bool expandLoad(const SIMemOpInfo &MOI,
                   MachineBasicBlock::iterator &MI);
   /// \brief Expands store operation \p MI. Returns true if instructions are
   /// added/deleted or \p MI is modified, false otherwise.
   bool expandStore(const SIMemOpInfo &MOI,
                    MachineBasicBlock::iterator &MI);
   /// \brief Expands atomic fence operation \p MI. Returns true if
   /// instructions are added/deleted or \p MI is modified, false otherwise.
   bool expandAtomicFence(const SIMemOpInfo &MOI,
                          MachineBasicBlock::iterator &MI);
   /// \brief Expands atomic cmpxchg or rmw operation \p MI. Returns true if
   /// instructions are added/deleted or \p MI is modified, false otherwise.
-  bool expandAtomicCmpxchg(const SIMemOpInfo &MOI,
+  bool expandAtomicCmpxchgOrRmw(const SIMemOpInfo &MOI,
                                 MachineBasicBlock::iterator &MI);
 
 public:
   static char ID;
 
   SIMemoryLegalizer() : MachineFunctionPass(ID) {}
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
Optional<SIMemOpInfo> SIMemOpInfo::getAtomicFenceInfo(
   SyncScope::ID SSID =
       static_cast<SyncScope::ID>(MI->getOperand(1).getImm());
   AtomicOrdering Ordering =
       static_cast<AtomicOrdering>(MI->getOperand(0).getImm());
   return SIMemOpInfo(SSID, Ordering);
 }
 
 /* static */
-Optional<SIMemOpInfo> SIMemOpInfo::getAtomicCmpxchgInfo(
+Optional<SIMemOpInfo> SIMemOpInfo::getAtomicCmpxchgOrRmwInfo(
     const MachineBasicBlock::iterator &MI) {
   assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
 
   if (!(MI->mayLoad() && MI->mayStore()))
     return None;
 
   // Be conservative if there are no memory operands.
   if (MI->getNumMemOperands() == 0)
     return SIMemOpInfo(SyncScope::System,
                        AtomicOrdering::SequentiallyConsistent,
                        AtomicOrdering::SequentiallyConsistent);
 
   return SIMemOpInfo::constructFromMIWithMMO(MI);
 }
 
 /* static */
 void SIMemOpInfo::reportUnknownSyncScope(
     const MachineBasicBlock::iterator &MI) {
   DiagnosticInfoUnsupported Diag(MI->getParent()->getParent()->getFunction(),
                                  "Unsupported synchronization scope");
   LLVMContext *CTX = &MI->getParent()->getParent()->getFunction().getContext();
   CTX->diagnose(Diag);
 }
 
-bool SIMemoryLegalizer::insertBufferWbinvl1Vol(MachineBasicBlock::iterator &MI,
-                                               bool Before) const {
+bool SIMemoryLegalizer::insertVmemSIMDCacheInvalidate(
+  MachineBasicBlock::iterator &MI, bool Before) const {
   MachineBasicBlock &MBB = *MI->getParent();
   DebugLoc DL = MI->getDebugLoc();
 
   if (!Before)
     ++MI;
 
-  BuildMI(MBB, MI, DL, TII->get(Wbinvl1Opcode));
+  BuildMI(MBB, MI, DL, TII->get(VmemSIMDCacheInvalidateOpc));
 
   if (!Before)
     --MI;
 
   return true;
 }
 
 bool SIMemoryLegalizer::insertWaitcntVmcnt0(MachineBasicBlock::iterator &MI,
if (MOI.getSSID() == SyncScope::System ||
         Changed |= enableGLCBit(MI);
 
       if (MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent)
         Changed |= insertWaitcntVmcnt0(MI);
 
       if (MOI.getOrdering() == AtomicOrdering::Acquire ||
           MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent) {
         Changed |= insertWaitcntVmcnt0(MI, false);
-        Changed |= insertBufferWbinvl1Vol(MI, false);
+        Changed |= insertVmemSIMDCacheInvalidate(MI, false);
       }
 
       return Changed;
     }
 
     if (MOI.getSSID() == SyncScope::SingleThread ||
         MOI.getSSID() == MMI->getWorkgroupSSID() ||
         MOI.getSSID() == MMI->getWavefrontSSID()) {
if (MOI.getSSID() == SyncScope::System ||
           MOI.getOrdering() == AtomicOrdering::Release ||
           MOI.getOrdering() == AtomicOrdering::AcquireRelease ||
           MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent)
         Changed |= insertWaitcntVmcnt0(MI);
 
       if (MOI.getOrdering() == AtomicOrdering::Acquire ||
           MOI.getOrdering() == AtomicOrdering::AcquireRelease ||
           MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent)
-        Changed |= insertBufferWbinvl1Vol(MI);
+        Changed |= insertVmemSIMDCacheInvalidate(MI);
 
       AtomicPseudoMIs.push_back(MI);
       return Changed;
     }
 
     if (MOI.getSSID() == SyncScope::SingleThread ||
         MOI.getSSID() == MMI->getWorkgroupSSID() ||
         MOI.getSSID() == MMI->getWavefrontSSID()) {
       AtomicPseudoMIs.push_back(MI);
       return Changed;
     }
 
     SIMemOpInfo::reportUnknownSyncScope(MI);
   }
 
   return Changed;
 }
 
-bool SIMemoryLegalizer::expandAtomicCmpxchg(const SIMemOpInfo &MOI,
-                                            MachineBasicBlock::iterator &MI) {
+bool SIMemoryLegalizer::expandAtomicCmpxchgOrRmw(const SIMemOpInfo &MOI,
   assert(MI->mayLoad() && MI->mayStore());
 
   bool Changed = false;
 
   if (MOI.isAtomic()) {
     if (MOI.getSSID() == SyncScope::System ||
         MOI.getSSID() == MMI->getAgentSSID()) {
       if (MOI.getOrdering() == AtomicOrdering::Release ||
           MOI.getOrdering() == AtomicOrdering::AcquireRelease ||
           MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent ||
           MOI.getFailureOrdering() == AtomicOrdering::SequentiallyConsistent)
         Changed |= insertWaitcntVmcnt0(MI);
 
       if (MOI.getOrdering() == AtomicOrdering::Acquire ||
           MOI.getOrdering() == AtomicOrdering::AcquireRelease ||
           MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent ||
           MOI.getFailureOrdering() == AtomicOrdering::Acquire ||
           MOI.getFailureOrdering() == AtomicOrdering::SequentiallyConsistent) {
         Changed |= insertWaitcntVmcnt0(MI, false);
-        Changed |= insertBufferWbinvl1Vol(MI, false);
+        Changed |= insertVmemSIMDCacheInvalidate(MI, false);
       }
 
       return Changed;
     }
 
     if (MOI.getSSID() == SyncScope::SingleThread ||
         MOI.getSSID() == MMI->getWorkgroupSSID() ||
         MOI.getSSID() == MMI->getWavefrontSSID()) {
bool SIMemoryLegalizer::runOnMachineFunction(MachineFunction &MF) {
   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
   const IsaInfo::IsaVersion IV = IsaInfo::getIsaVersion(ST.getFeatureBits());
 
   MMI = &MF.getMMI().getObjFileInfo<AMDGPUMachineModuleInfo>();
   TII = ST.getInstrInfo();
 
   Vmcnt0Immediate =
       AMDGPU::encodeWaitcnt(IV, 0, getExpcntBitMask(IV), getLgkmcntBitMask(IV));
-  Wbinvl1Opcode = ST.getGeneration() <= AMDGPUSubtarget::SOUTHERN_ISLANDS ?
+  VmemSIMDCacheInvalidateOpc =
+     ST.getGeneration() <= AMDGPUSubtarget::SOUTHERN_ISLANDS ?
        AMDGPU::BUFFER_WBINVL1 : AMDGPU::BUFFER_WBINVL1_VOL;
 
   for (auto &MBB : MF) {
     for (auto MI = MBB.begin(); MI != MBB.end(); ++MI) {
       if (!(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic))
         continue;
 
       if (const auto &MOI = SIMemOpInfo::getLoadInfo(MI))
         Changed |= expandLoad(MOI.getValue(), MI);
       else if (const auto &MOI = SIMemOpInfo::getStoreInfo(MI))
         Changed |= expandStore(MOI.getValue(), MI);
       else if (const auto &MOI = SIMemOpInfo::getAtomicFenceInfo(MI))
         Changed |= expandAtomicFence(MOI.getValue(), MI);
-      else if (const auto &MOI = SIMemOpInfo::getAtomicCmpxchgInfo(MI))
-        Changed |= expandAtomicCmpxchg(MOI.getValue(), MI);
+      else if (const auto &MOI = SIMemOpInfo::getAtomicCmpxchgOrRmwInfo(MI))
+        Changed |= expandAtomicCmpxchgOrRmw(MOI.getValue(), MI);
     }
   }
 
   Changed |= removeAtomicPseudoMIs();
   return Changed;
 }
 
 INITIALIZE_PASS(SIMemoryLegalizer, DEBUG_TYPE, PASS_NAME, false, false)
 
 char SIMemoryLegalizer::ID = 0;
 char &llvm::SIMemoryLegalizerID = SIMemoryLegalizer::ID;
 
 FunctionPass *llvm::createSIMemoryLegalizerPass() {
   return new SIMemoryLegalizer();
 }