[AMDGPU] removed dead code handling rmw in memory legalizer

[rampitec]

Summary

It was always using cmpxchg path and in rmw and cmpxchg instructions
are not distinguishable in the BE.

[kzhuravl]

LGTM with minor nit.

lib/Target/AMDGPU/SIMemoryLegalizer.cpp

110

Move to previous line.

[rampitec]

Comment formatting.

lib/Target/AMDGPU/SIMemoryLegalizer.cpp

static Optional<SIMemOpInfo> getLoadInfo(
       const MachineBasicBlock::iterator &MI);
   /// \returns Store info if \p MI is a store operation, "None" otherwise.
   static Optional<SIMemOpInfo> getStoreInfo(
       const MachineBasicBlock::iterator &MI);
   /// \returns Atomic fence info if \p MI is an atomic fence operation,
   /// "None" otherwise.
   static Optional<SIMemOpInfo> getAtomicFenceInfo(
       const MachineBasicBlock::iterator &MI);
-  /// \returns Atomic cmpxchg info if \p MI is an atomic cmpxchg operation,
+  /// \returns Atomic cmpxchg/rmw info if \p MI is an atomic cmpxchg or
+  /// rmw operation,
   /// "None" otherwise.
   static Optional<SIMemOpInfo> getAtomicCmpxchgInfo(
       const MachineBasicBlock::iterator &MI);
-  /// \returns Atomic rmw info if \p MI is an atomic rmw operation,
-  /// "None" otherwise.
-  static Optional<SIMemOpInfo> getAtomicRmwInfo(
-      const MachineBasicBlock::iterator &MI);
 
   /// \brief Reports unknown synchronization scope used in \p MI to LLVM
   /// context.
   static void reportUnknownSyncScope(
       const MachineBasicBlock::iterator &MI);
 };
 
 class SIMemoryLegalizer final : public MachineFunctionPass {
private:
   /// \brief Expands store operation \p MI. Returns true if instructions are
   /// added/deleted or \p MI is modified, false otherwise.
   bool expandStore(const SIMemOpInfo &MOI,
                    MachineBasicBlock::iterator &MI);
   /// \brief Expands atomic fence operation \p MI. Returns true if
   /// instructions are added/deleted or \p MI is modified, false otherwise.
   bool expandAtomicFence(const SIMemOpInfo &MOI,
                          MachineBasicBlock::iterator &MI);
-  /// \brief Expands atomic cmpxchg operation \p MI. Returns true if
+  /// \brief Expands atomic cmpxchg or rmw operation \p MI. Returns true if
   /// instructions are added/deleted or \p MI is modified, false otherwise.
   bool expandAtomicCmpxchg(const SIMemOpInfo &MOI,
                            MachineBasicBlock::iterator &MI);
-  /// \brief Expands atomic rmw operation \p MI. Returns true if
-  /// instructions are added/deleted or \p MI is modified, false otherwise.
-  bool expandAtomicRmw(const SIMemOpInfo &MOI,
-                       MachineBasicBlock::iterator &MI);
 
 public:
   static char ID;
 
   SIMemoryLegalizer() : MachineFunctionPass(ID) {}
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
if (MI->getNumMemOperands() == 0)
     return SIMemOpInfo(SyncScope::System,
                        AtomicOrdering::SequentiallyConsistent,
                        AtomicOrdering::SequentiallyConsistent);
 
   return SIMemOpInfo::constructFromMIWithMMO(MI);
 }
 
 /* static */
-Optional<SIMemOpInfo> SIMemOpInfo::getAtomicRmwInfo(
-    const MachineBasicBlock::iterator &MI) {
-  assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
-
-  if (!(MI->mayLoad() && MI->mayStore()))
-    return None;
-
-  // Be conservative if there are no memory operands.
-  if (MI->getNumMemOperands() == 0)
-    return SIMemOpInfo(SyncScope::System,
-                       AtomicOrdering::SequentiallyConsistent);
-
-  return SIMemOpInfo::constructFromMIWithMMO(MI);
-}
-
-/* static */
 void SIMemOpInfo::reportUnknownSyncScope(
     const MachineBasicBlock::iterator &MI) {
   DiagnosticInfoUnsupported Diag(MI->getParent()->getParent()->getFunction(),
                                  "Unsupported synchronization scope");
   LLVMContext *CTX = &MI->getParent()->getParent()->getFunction().getContext();
   CTX->diagnose(Diag);
 }
 
if (MOI.isAtomic()) {
     }
 
     llvm_unreachable("Unsupported synchronization scope");
   }
 
   return Changed;
 }
 
-bool SIMemoryLegalizer::expandAtomicRmw(const SIMemOpInfo &MOI,
-                                        MachineBasicBlock::iterator &MI) {
-  assert(MI->mayLoad() && MI->mayStore());
-
-  bool Changed = false;
-
-  if (MOI.isAtomic()) {
-    if (MOI.getSSID() == SyncScope::System ||
-        MOI.getSSID() == MMI->getAgentSSID()) {
-      if (MOI.getOrdering() == AtomicOrdering::Release ||
-          MOI.getOrdering() == AtomicOrdering::AcquireRelease ||
-          MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent)
-        Changed |= insertWaitcntVmcnt0(MI);
-
-      if (MOI.getOrdering() == AtomicOrdering::Acquire ||
-          MOI.getOrdering() == AtomicOrdering::AcquireRelease ||
-          MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent) {
-        Changed |= insertWaitcntVmcnt0(MI, false);
-        Changed |= insertBufferWbinvl1Vol(MI, false);
-      }
-
-      return Changed;
-    }
-
-    if (MOI.getSSID() == SyncScope::SingleThread ||
-        MOI.getSSID() == MMI->getWorkgroupSSID() ||
-        MOI.getSSID() == MMI->getWavefrontSSID()) {
-      Changed |= enableGLCBit(MI);
-      return Changed;
-    }
-
-    llvm_unreachable("Unsupported synchronization scope");
-  }
-
-  return Changed;
-}
-
 bool SIMemoryLegalizer::runOnMachineFunction(MachineFunction &MF) {
   bool Changed = false;
   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
   const IsaInfo::IsaVersion IV = IsaInfo::getIsaVersion(ST.getFeatureBits());
 
   MMI = &MF.getMMI().getObjFileInfo<AMDGPUMachineModuleInfo>();
   TII = ST.getInstrInfo();
 
for (auto MI = MBB.begin(); MI != MBB.end(); ++MI) {
       if (const auto &MOI = SIMemOpInfo::getLoadInfo(MI))
         Changed |= expandLoad(MOI.getValue(), MI);
       else if (const auto &MOI = SIMemOpInfo::getStoreInfo(MI))
         Changed |= expandStore(MOI.getValue(), MI);
       else if (const auto &MOI = SIMemOpInfo::getAtomicFenceInfo(MI))
         Changed |= expandAtomicFence(MOI.getValue(), MI);
       else if (const auto &MOI = SIMemOpInfo::getAtomicCmpxchgInfo(MI))
         Changed |= expandAtomicCmpxchg(MOI.getValue(), MI);
-      else if (const auto &MOI = SIMemOpInfo::getAtomicRmwInfo(MI))
-        Changed |= expandAtomicRmw(MOI.getValue(), MI);
     }
   }
 
   Changed |= removeAtomicPseudoMIs();
   return Changed;
 }
 
 INITIALIZE_PASS(SIMemoryLegalizer, DEBUG_TYPE, PASS_NAME, false, false)
 
 char SIMemoryLegalizer::ID = 0;
 char &llvm::SIMemoryLegalizerID = SIMemoryLegalizer::ID;
 
 FunctionPass *llvm::createSIMemoryLegalizerPass() {
   return new SIMemoryLegalizer();
 }