[ARM] FP16 mov imm pattern

[SjoerdMeijer]

Summary

This is a follow up of r324321, adding a match pattern for mov
with a FP16 immediate (also fixing operand vfp_f16imm that wasn't
even compiling).

[samparker]

LGTM, cheers!

llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

 }
 
 def vfp_f16imm : Operand<f16>,
                  PatLeaf<(f16 fpimm), [{
       return ARM_AM::getFP16Imm(N->getValueAPF()) != -1;
     }], SDNodeXForm<fpimm, [{
       APFloat InVal = N->getValueAPF();
       uint32_t enc = ARM_AM::getFP16Imm(InVal);
-      return CurDAG->getTargetConstant(enc, MVT::i32);
+      return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
     }]>> {
   let PrintMethod = "printFPImmOperand";
   let ParserMatchClass = FPImmOperand;
 }
 
 def vfp_f32imm : Operand<f32>,
                  PatLeaf<(f32 fpimm), [{
       return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
   let Inst{19-16} = imm{7-4};
   let Inst{15-12} = Sd{4-1};
   let Inst{11-9}  = 0b101;
   let Inst{8}     = 0;          // Single precision.
   let Inst{7-4}   = 0b0000;
   let Inst{3-0}   = imm{3-0};
 }
 
-def FCONSTH : VFPAI<(outs SPR:$Sd), (ins vfp_f16imm:$imm),
+def FCONSTH : VFPAI<(outs HPR:$Sd), (ins vfp_f16imm:$imm),
                      VFPMiscFrm, IIC_fpUNA16,
                      "vmov", ".f16\t$Sd, $imm",
-                     []>, Requires<[HasFullFP16]> {
+                     [(set HPR:$Sd, vfp_f16imm:$imm)]>,
+              Requires<[HasFullFP16]> {
   bits<5> Sd;
   bits<8> imm;
 
   let Inst{27-23} = 0b11101;
   let Inst{22}    = Sd{0};
   let Inst{21-20} = 0b11;
   let Inst{19-16} = imm{7-4};
   let Inst{15-12} = Sd{4-1};

llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll

 
 ; CHECK-LABEL:                 VMLS:
 ; CHECK-HARDFP-FULLFP16:       vmls.f16  s2, s0, s1
 ; CHECK-HARDFP-FULLFP16-NEXT:  vmov.f32  s0, s2
 }
 
 ; TODO: fix immediates.
 ; 21. VMOV (between general-purpose register and half-precision register)
+
 ; 22. VMOV (immediate)
+define i32 @movi(i32 %a.coerce) {
+entry:
+  %tmp.0.extract.trunc = trunc i32 %a.coerce to i16
+  %0 = bitcast i16 %tmp.0.extract.trunc to half
+  %add = fadd half %0, 0xHC000
+  %1 = bitcast half %add to i16
+  %tmp2.0.insert.ext = zext i16 %1 to i32
+  ret i32 %tmp2.0.insert.ext
+
+; CHECK-LABEL:            movi:
+; CHECK-HARDFP-FULLFP16:  vmov.f16  s0, #-2.000000e+00
+}
 
 ; 23. VMUL
 define float @Mul(float %a.coerce, float %b.coerce) {
 entry:
   %0 = bitcast float %a.coerce to i32
   %tmp.0.extract.trunc = trunc i32 %0 to i16
   %1 = bitcast i16 %tmp.0.extract.trunc to half
   %2 = bitcast float %b.coerce to i32